1M mode "quirk"

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Chilly Willy
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1M mode "quirk"

Post by Chilly Willy » Sun Jul 29, 2012 2:16 am

I ran across something strange (to me, at least) when working on the CD DMA Color demo over in the demos forum. In 1M mode, you have one 128KB block of ram addressable by the CD, and another 128KB block of ram addressable by the MD. While in that mode, the SEGA CD manual says the following:

The MD side is the only side that can write bit 1 of the memory mode control register. When it write a 1 to the bit, it requests a bank switch. It stays a 1 until the CD side switches banks, and then goes to 0 when the banks are fully switched. The CD side is the only side that can write bit 0. When it does, the value of the bit determines which bank each side can address. To switch banks, the CD side toggles bit 0.

And from my experiments on the demo, the explanation for bit 1 is complete garbage. It does nothing at all that I can detect. Bit 0 acts as described - changing it changes the banks, but bit 1 seems to always be 0. I took a quick look at the SEGA example code for the CD, and when they wish to request a bank switch from the MD side, they do NOT set bit 1 of the memory control, they set some arbitrarily chosen bit in one of the communication registers. The CD side looks for that bit in the comm regs and switches the banks.

So SEGA themselves don't go by what the manual says. This same explanation is in both the hardware and the software manuals. There is nothing about it being wrong in any of the addendums or tech bulletins. But the example code avoids it, and my own experiments seem to indicate it doesn't work the way the manuals say.

Has anyone else run into this?

bgvanbur
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Post by bgvanbur » Sun Jul 29, 2012 3:00 am

The Cinepak code also does this (MAIN sets comm bit to indicate to SUB done with 1M and ready for next frame and SUB does the switch when ready).

Eke
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Post by Eke » Sun Jul 29, 2012 7:54 am

Yes, it was discussed some time ago in another thread here. The DMNA bit must be set to 0 (not 1) to request word-ram bank switching (it is read as 1 after that, until the switch has been performed by sub-cpu).
I actually found this to be correctly explained in only one place of the available documentation (main-cpu section of "rex sabio" hardware manual), in other places it is either wrong ("writing 1 to dmna bit") or imprecise ("on read, dmna bit is set to 1"), which probably did not help during manuals translation.

Chilly Willy
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Post by Chilly Willy » Sun Jul 29, 2012 5:40 pm

Thanks! I'll have to try that. I'd have probably never guessed writing a "0" to get a "1" result. :lol:

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