FIFO
Moderator: BigEvilCorporation
FIFO
Hi you all.
Still on 32x dev' ;)
I'm looking at the FIFO. First of all, is it usable ? Or is it DREQ only ?
The 68k writes to A1 5112h, and the SH2s read 2000 4012h. But is it a stack, a heap or anything ? And if so, how big is it ?
I mean, if the 68k want to put several datas, does it have to wait the SH2s to grab the data in the FIFO for each value ?
Still on 32x dev' ;)
I'm looking at the FIFO. First of all, is it usable ? Or is it DREQ only ?
The 68k writes to A1 5112h, and the SH2s read 2000 4012h. But is it a stack, a heap or anything ? And if so, how big is it ?
I mean, if the 68k want to put several datas, does it have to wait the SH2s to grab the data in the FIFO for each value ?
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Re: FIFO
I don't remember exactly how it work but you have a software method (the 68k keep writing the FIFO reg during the SH2 keep reading it) and a hardware one (main SH2 DMA unit is used)... it's a bit complexe to use them. Why don't use the communication buffer ? It's still the best and easiest way to exchange quickly small amount of data.ob1 wrote:Hi you all.
Still on 32x dev'
I'm looking at the FIFO. First of all, is it usable ? Or is it DREQ only ?
The 68k writes to A1 5112h, and the SH2s read 2000 4012h. But is it a stack, a heap or anything ? And if so, how big is it ?
I mean, if the 68k want to put several datas, does it have to wait the SH2s to grab the data in the FIFO for each value ?
Re: FIFO
For small data, I agree. But what about bigger data ? Anyway, I think I understand how the FIFO runs. The DMA remais a bit unclear for now, but it's going to change soon ;)Stef wrote:It's still the best and easiest way to exchange quickly small amount of data.
Anyway, how big is the FIFO ? I've only found this assumption in cpu_sh2.c :
Code: Select all
memset (_32X_FIFO_A, 0, 4 * 2);
OK, so I've done a little 32X ROM, with just the 68k running. Here's the code :
or, for you Cish guys,
and guess what ... d1 = 8 !!!
So, FIFO is 8 16-bit words long ?
Code: Select all
start68k:
move.l #$A15106,a0 ; DREQ Control Register
move.l #$A15112,a1 ; FIFO Register
move.w #4,(a0) ; CPU write (68k writes data in FIFO)
moveq #0,d1
whileFIFONotFull:
move.w (a0),d0
andi.w #$80,d0
bne FIFOFull
move.w d1,(a1)
addq #1,d1
bra whileFIFONotFull
FIFOFull:
bra FIFOFull
end68k:
Code: Select all
int main() {
int * FIFO_CTRL_REG = (int *) 0xA15106;
int * FIFO_REG = (int *) 0xA15112;
int FIFO_FULL = 0x80;
int i=0;
while (!(*FIFO_CTRL_REG & FIFO_FULL)) {
*FIFO_REG = i;
i++;
}
}
So, FIFO is 8 16-bit words long ?
I ask on DevSter : http://devster.proboards22.com/index.cg ... 1170758649
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- Very interested
- Posts: 3131
- Joined: Thu Nov 30, 2006 9:46 pm
- Location: France - Sevres
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Gens can be wrong, it should not really impact on compatibility.ob1 wrote:I ask on DevSter : http://devster.proboards22.com/index.cg ... 1170758649
Did you tried your bit of code on Gens ?