DMA and cache
Posted: Sun Feb 28, 2010 9:58 am
Wandering on Bit-Blit, I asked myself something I could not answer.
When reading SDRAM from SH2, reads are done by 8 16-bits words burts, due or for the cache. But how does this run for DMA ?
SH2 has a DMAc, which is mainly used for DREQ, from 68k to 32X, or for PWM (never really used if I got it right).
Anyway, in the case of an intra-32X DMA operation, for example, to copy data from SDRAM to Frame Buffer DRAM, does the DMA read 8 16-bits words burst, even if it just need, let's say 8 bytes ?
When reading SDRAM from SH2, reads are done by 8 16-bits words burts, due or for the cache. But how does this run for DMA ?
SH2 has a DMAc, which is mainly used for DREQ, from 68k to 32X, or for PWM (never really used if I got it right).
Anyway, in the case of an intra-32X DMA operation, for example, to copy data from SDRAM to Frame Buffer DRAM, does the DMA read 8 16-bits words burst, even if it just need, let's say 8 bytes ?