DMA and cache

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DMA and cache

Post by ob1 » Sun Feb 28, 2010 9:58 am

Wandering on Bit-Blit, I asked myself something I could not answer.
When reading SDRAM from SH2, reads are done by 8 16-bits words burts, due or for the cache. But how does this run for DMA ?
SH2 has a DMAc, which is mainly used for DREQ, from 68k to 32X, or for PWM (never really used if I got it right).
Anyway, in the case of an intra-32X DMA operation, for example, to copy data from SDRAM to Frame Buffer DRAM, does the DMA read 8 16-bits words burst, even if it just need, let's say 8 bytes ?

Chilly Willy
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Post by Chilly Willy » Sun Feb 28, 2010 6:39 pm

Read the SH7604 Hardware Manual, sections 7.5.3 and 7.5.4. Basically, "bursts" work for 16 byte reads on 16 byte aligned addresses. Cache line fills always fit those requirements, so they always use burst mode. DMA reads will only fit that requirement if the buffer is on a 16 byte boundary, is multiples of 16 bytes, and you use 16 byte mode for the xfer. When you do all that, DMA also uses "burst" mode for reading the data.

Note that the 32X has the SDRAM set for burst mode. This gives rise to wasted cycles on "single reads" as documented in 7.5.4. While burst mode speeds up cache line fetches, single reads can waste six or seven cycles on the bus (8 word bus operations, of which only one or two actually contain useful data). Cache-through reads and DMA operations that don't fit burst mode are single reads, and waste bus cycles as described.

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