I hate to "raise topics from their grave", but I really hope you dear reader will find some resources of interest in this post.
So, regarding memory type, here are the Bus State Controler settings made in BIOS :
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value_offset_348h: DC.L $A55A0001 ; BCR1
Bus Control Register 1 (FFFF FFE0)
- Master, Big-endian, Area0 is accessed normally,
- No partial space share specification
- 3 waits for areas 0-3
- Area 2 is ordinary space, area 3 is SDRAM
NB : 'A55A is irrelevant
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value_offset_34Ch: DC.L $A55A00A8 ; BCR2
Bus Control Register 1 (FFFF FFE4)
Area 0-3 are word (16-bit) size
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value_offset_350h DC.L $A55A0055 ; WCR
Wait Control Register (FFFF FFE8)
No idle cycle for areas 0-3, CAS Latency 2 cycles
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value_offset_354h DC.L $A55A0AB8 MCR
Individual Memory Control Register (FFFF FFEC)
- RAS Precharge Time (TRP) : 1 cycle
- RAS-CAS Delay (RCD) : 1 cycle
- Write-Precharge Delay (TRWL) : 1 cycle
- RMD - Refresh Mode (RMODE). When the RFSH bit is 1 and this bit is 0, a CAS-before-RAS refresh or auto-refresh is performed at the interval set in the 8-bit interval timer.
- RFSH - Refresh Control. This bit determines whether or not the refresh operation of DRAM/synchronous DRAM/pseudo-SRAM is performed. This bit is not valid in the slave mode and is always handled as 0.
- AMX - For SDRAM itnerface : 2-Mbit DRAM (128k x 16 bits)
- SZ - For synchronous DRAM, DRAM, and pseudo-SRAM space, the data bus width of BCR2 is ignored in favor of the specification of this bit ==> Word
- RASD - For synchronous DRAM, access ends in the bank active state. This is only valid for area 3. When area 2 is synchronous DRAM, the mode is always auto-precharge.
- BE - Burst (fast-page mode) disabled (initial value). During SDRAM access, burst operation is always enabled regardless of this bit*.
- TRAS - CAS-before-RAS Refresh RAS Assert Time : 3 cycles
- TRWL - Write-Precharge Delay (TRWL) : 1 cycle
- RCD - RAS-CAS Delay (RCD) : 1 cycle
- TRP - RAS Precharge Time (TRP) : 1 cycle
* : OK, this one is interesting. You see, for a long time, I've tried to enable fast page mode on the VRAM/DRAM. I thought the secret to enable it was in the BIOS. And sure it was. BUT :
- once the memory settings are done, you can't rewrite them without a reset
- I suspect this bit only concern Area 3 and, as stated in BCR1, area 3 is SDRAM.
- last but no list, VRAM/DRAM is not connected to the SH2s, but to a DAC (315-5781) which itself is connected to the 32X interface (315-5818). So there is absolutely no way to "connect" more directly with the VRAM/DRAM.
So, I guess we'll have to stick to the BIOS settings, forever and ever.
Oh, and the CAS latency set in the WCR (2) matches the µPD4502161 SDRAM settings.
