SH2 SCI

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ob1
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SH2 SCI

Post by ob1 » Tue Jan 20, 2009 10:40 am

I'd like to write about SH2 SCI : Serial Communication Interface.
It's a way to make both CPU communicate.
SCI allows asynchronous and synchronous modes.
The 32X Hardware Manual states that "Serial communication is connected between the master and slave. Because the serial clock is also connected, it can be used in clock synchronization if one side outputs and the other side inputs." (p85)
For example, the Master puts its internal serial clock as a external serial clock for the slave, thus enabling Synchronous serial mode.

The SCI is duplex.

Then, the formula given by the SH2 Hardware Manual says :
B =10^6 x freq / ( 32 x 2^(2n-1) x (N+1) )
where B is the bitrate, in bits/s,
freq is the SH2 frequency, in MHz,
n is set by CKS1 and CKS0 bits in the Serial Mode Register, 0<=CKS<=3
N is set by the Bit Rate Register, 0<=N<=255

The 32X Hardware Manual defines the SH2 frequencies as follow :
SH2 freq = 3/7 x 68k freq,
thus 22.801 MHz [PAL] and 23MHz [NTSC] (p54)

So, the maximum that can theorically be achieved is on a PAL system with n=0 and N=0 ~ 1.4Mb/s. Unfortunately, the SH2 Hardware Manual says that in this case , "Continuous transmission/reception not possible". I guess that it's because the clock is too fast, and CPU can not tell when a high level is still a clock or a stop.
Moreover, the SH2 Hardware Manual is note very precise when freq lies between 16 and 28.7 MHz. Unfortunately, this is our case !!! "Some errors could occur" :(
Finally, we can definitely achieve 100kb/s, which is not that much.

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