Contention Between Instruction Fetch and Memory Access

[ob1]

Hello to you all.
Working on a personal project, I eventually benchmarked the contention between Instruction Fetch (IF) and Memory Access (MA), as described in §7.4 of the Hitachi SH2 Programming Manual, and especially §7.4.3 : Relationship Between Position of Instructions Located in On-Chip ROM/RAM or On-Chip Memory and Contention Between IF and MA.

My test is thereafter:

Code: Select all

!loop:
	MOV.W	R12,@R1
	ADD	#1,R9
	CMP/HI	R9,R13
	BF/S	!rarely
	ADD	#2,R1
	DT	R11
	BF/S	!loop
	MOV.W	@R10+,R12

I aligned this code on address 4n, then 4n+2, thus testing contention between IF of last line, and MA of first line.
The results : contention between IF and MA slows down the code between 4 and 8%.
This loop is in an outer loop, so, your mileage may vary.
Tested on real PAL hardware.

I thought this could help ^^