SH2 DMA

ob1 · Post by **ob1** » Thu Mar 29, 2007 8:56 am

Hello.
You all know the 32X can perform DMA, either from FIFO port to memory or to PWM. But did you know each CPU could also perform DMA ?
Here's what you need to set (in this example, I'd use DMA1, the 2nd DMA channel) :
SAR1 (FFFF FF90h) : source address, in SH2 memory map
DAR1 (FFFF FF94h) : destination address, in SH2 memory map
TCR1 (FFFF FF98h) : transfer count, in 16-bit words(*) unit
CHCR1 (FFFF FF9Ch) : Channel Control, please don't listen to SEGA and put 56E1h instead (Thank you very much Stef').
Then, start DMA by writing 1 into DMAOR (FFFF FFB0h).

Access all registers in longword units.

* : you can also transfer in byte (useless), longword (32-bits) and 16-byte unit. Set CHCR TS bits.

For example, I want to copy 256 16-bit words from 2200 0814h (814h on the ROM cartridge) to Frame Buffer 0h (right, I want to initialize the line table) :

Code: Select all

	mov.l	LTInit3_DMA1,R1
	mov.l	LTInit3_Pattern,R0
	mov.l	R0,@R1		; SAR1
	mov.l	LTInit3_FB,R0
	mov.l	R0,@(4,R1)	; DAR1
	mov.w	LTInit3_SIZE,R0
	mov.l	R0,@($8,R1)	; TCR1
	mov.w	LTInit3_CHCR,R0
	mov.l	R0,@($C,R1)	; CHCR1
	mov.l	@R1,R0
	mov.l	LTInit3_DMAOR,R1
	mov	#1,R0
	mov.l	R0,@R1		; Start DMA
	rts
	nop
	.align	4
LTInit3_DMA1:	dc.l	$FFFFFF90
LTInit3_DMAOR:	dc.l	$FFFFFFB0
LTInit3_Pattern:	dc.l	$22000814
LTInit3_FB:	dc.l	$24000000
LTInit3_SIZE:	dc.w	$0100	; 256 16-bit words
LTInit3_CHCR:	dc.w	$56E1

Stay tuned for speed performance.

ob1 · Post by **ob1** » Fri Mar 30, 2007 9:08 am

Looks like the DMA take 8 cycles to perform, regardless of the total bytes to transfer.
It seems very fast, too fast actually, regarding to me. Anyway, I guess I can cope with it.
It isn't clear whetever the CPU is stalled during DMA. But the other CPU is actually running.

Fonzie · Post by **Fonzie** » Fri Mar 30, 2007 9:18 am

wouldn't the cpu making dma still running but at slower speed? It would be great

Stef · Post by **Stef** » Fri Mar 30, 2007 2:17 pm

ob1 wrote:Looks like the DMA take 8 cycles to perform, regardless of the total bytes to transfer.
It seems very fast, too fast actually, regarding to me. Anyway, I guess I can cope with it.
It isn't clear whetever the CPU is stalled during DMA. But the other CPU is actually running.

I don't stop the SH-2 cpu during DMA in Gens so i guess they work in "cycle steal" mode (or i would have done that in a different way).

ob1 · Post by **ob1** » Fri Mar 30, 2007 2:30 pm

The CHCR TB bit (bit 4) is set to cycle-steal mode.
The CPU thus must be still active.

Fonzie · Post by **Fonzie** » Fri Mar 30, 2007 2:34 pm

That's great

And maybe it still run at fullspeed when you're running from cache

Mask of Destiny · Post by **Mask of Destiny** » Fri Mar 30, 2007 2:35 pm

AFAIK, even when the DMA engine is set to completely take over the bus, the CPU can still execute code out of cache.

ob1 · Post by **ob1** » Fri Mar 30, 2007 2:46 pm

That would seem logic to me : the buses (RAM, DMA and cache) are independant.