32X memory type

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ob1
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32X memory type

Post by ob1 » Tue Jan 20, 2009 2:50 pm

Hi you all.
I'm messing around with the 32X internals. That's funny cause I don't have it !
Anyway, I'd like to know if any of you has already heard of the type of memory that are used.
We all know that main memory is 256kB SDRAM and FrameBuffer is 2 x 128kB DRAM.
What I think is that SDRAM and DRAM are both is 128k x 16 bits.
The Master Boot ROM tells me the SDRAM CAS latency is 2.
What I don't know is timings (60ns ?), precise latencies for SDRAM, and DRAM type (FPM DRAM ?). Especially, the FPM would allow to enable the Burst Access from the SH2.

So, anything anyone ?

TmEE co.(TM)
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Post by TmEE co.(TM) » Tue Jan 20, 2009 5:17 pm

The frame buffers are 80ns 1Mbit DRAMs of some flavour, possibly FPM but I'm not sure.
SDRAM is a single SDRAM chip which specs I don't remember...
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TmEE co.(TM)
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Post by TmEE co.(TM) » Mon Jan 26, 2009 9:56 pm

The framebuffers are 80ns 1Mbit Fast Page Mode DRAMs. Datasheet (in Japanese) is here : http://www.digchip.com/datasheets/downl ... 21664AM-80

Someone at gamesx.com happened to look for these chips so I grabbed the datasheet link :P
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Post by Jorge Nuno » Mon Jan 26, 2009 10:13 pm

In EN:

http://trapalhadas.no.sapo.pt/lc321664.pdf 8)

Standard FPM DRAM with selectable byte writes...

For the guy looking for theese chips, any faster DRAM equal or bigger than 64k*16 with separated WEs instead of separated CASs will do, just tie the extra addresses to gnd or vcc.

One example: µPD424170 (1024rows*256columns*16bit, FPM, UWE+LWE)
though this one won't fit directly because the OE/CAS/A0-9 are shifted around

ob1
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Post by ob1 » Tue Jan 27, 2009 12:49 pm

TmEE co.(TM) wrote:The framebuffers are 80ns 1Mbit Fast Page Mode DRAMs
ob1 wrote:Especially, the FPM would allow to enable the Burst Access from the SH2.
SH2 Hardware Manual states
DRAM also has a high-speed page mode (...) by changing only the column address after the row address is output
Burst Write Access is shown in memory module datasheet, p19.
Burst Access is enabled using bit BE in MCR[10], $FFFF FFEC

Enabling Burst Access, you could theorically write 256 16-bits words by issuing only one row address.
Beware : exclusive access. If the Slave is writing using Burst Access, the Master will take the bus whenever he wants to read/write, thus breaking the burst access.

Thank you TmEE and Jorge Nuno.
Olivier

ob1
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Re: 32X memory type

Post by ob1 » Mon Nov 23, 2020 9:10 pm

I hate to "raise topics from their grave", but I really hope you dear reader will find some resources of interest in this post.
So, regarding memory type, here are the Bus State Controler settings made in BIOS :

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value_offset_348h:	DC.L	$A55A0001	; BCR1
Bus Control Register 1 (FFFF FFE0)
  • Master, Big-endian, Area0 is accessed normally,
  • No partial space share specification
  • 3 waits for areas 0-3
  • Area 2 is ordinary space, area 3 is SDRAM
NB : 'A55A is irrelevant

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value_offset_34Ch:	DC.L	$A55A00A8	; BCR2
Bus Control Register 1 (FFFF FFE4)
Area 0-3 are word (16-bit) size

Code: Select all

value_offset_350h	DC.L	$A55A0055	; WCR
Wait Control Register (FFFF FFE8)
No idle cycle for areas 0-3, CAS Latency 2 cycles

Code: Select all

value_offset_354h	DC.L	$A55A0AB8	MCR
Individual Memory Control Register (FFFF FFEC)
  • RAS Precharge Time (TRP) : 1 cycle
  • RAS-CAS Delay (RCD) : 1 cycle
  • Write-Precharge Delay (TRWL) : 1 cycle
  • RMD - Refresh Mode (RMODE). When the RFSH bit is 1 and this bit is 0, a CAS-before-RAS refresh or auto-refresh is performed at the interval set in the 8-bit interval timer.
  • RFSH - Refresh Control. This bit determines whether or not the refresh operation of DRAM/synchronous DRAM/pseudo-SRAM is performed. This bit is not valid in the slave mode and is always handled as 0.
  • AMX - For SDRAM itnerface : 2-Mbit DRAM (128k x 16 bits)
  • SZ - For synchronous DRAM, DRAM, and pseudo-SRAM space, the data bus width of BCR2 is ignored in favor of the specification of this bit ==> Word
  • RASD - For synchronous DRAM, access ends in the bank active state. This is only valid for area 3. When area 2 is synchronous DRAM, the mode is always auto-precharge.
  • BE - Burst (fast-page mode) disabled (initial value). During SDRAM access, burst operation is always enabled regardless of this bit*.
  • TRAS - CAS-before-RAS Refresh RAS Assert Time : 3 cycles
  • TRWL - Write-Precharge Delay (TRWL) : 1 cycle
  • RCD - RAS-CAS Delay (RCD) : 1 cycle
  • TRP - RAS Precharge Time (TRP) : 1 cycle
* : OK, this one is interesting. You see, for a long time, I've tried to enable fast page mode on the VRAM/DRAM. I thought the secret to enable it was in the BIOS. And sure it was. BUT :
  • once the memory settings are done, you can't rewrite them without a reset
  • I suspect this bit only concern Area 3 and, as stated in BCR1, area 3 is SDRAM.
  • last but no list, VRAM/DRAM is not connected to the SH2s, but to a DAC (315-5781) which itself is connected to the 32X interface (315-5818). So there is absolutely no way to "connect" more directly with the VRAM/DRAM.
So, I guess we'll have to stick to the BIOS settings, forever and ever.

Oh, and the CAS latency set in the WCR (2) matches the µPD4502161 SDRAM settings.

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