The Comm Port is visible from Genesis side at A1 5120h and from 32X side at 2000 4020h.
The Comm Port needs a status flag to ensure synchronization. The Comm Port status has five states :
WRITE_ME. The 68k can write to the Comm Port.
WRITING. The 68k is writing to the Comm Port. This port is more or less useless, since there's only one processor (the 68k) that can write to the Comm Port with this configuration.
READ_ME. The Comm Port can be read by one SH2.
READING_M. The Master SH2 is reading the Comm Port.
READING_S. The Slave SH2 is reading the Comm Port.
Here's the code for the 68k to write something to the Comm Port :
Code: Select all
void putVDP(int ctrl, int data0, int data1, ...) {
while (COMM_PORT(STATUS) != WRITE_ME) ;
COMM_PORT(STATUS) = WRITING;
// write data
COMM_PORT(STATUS) = READ_ME;
}
Code: Select all
READING_M equ 3
READING_S equ 4
MASTER_INIT: ; at 3D0h, set the Master SH2 to start from here
; set cache as 2way
MOV READ_STATUS,R1
MOV READING_M,@R1
BRA MAIN
SLAVE_INIT: ; at 3D4h, set the Slave SH2 to start from here
; set cache as 2way
MOV READ_STATUS,R1
MOV READING_S,@R1
BRA MAIN
READ_STATUS:
dc.l $C0000000
MAIN:
; 32X SH2 main code
Code: Select all
void readVDP() {
int * READ_STATUS = (int *) 0xC0000000;
int entrance = 1;
while (entrance | COMM_PORT(STATUS)==*READ_STATUS) {
entrance = 0;
while (COMM_PORT(STATUS) != READ_ME) ;
COMM_PORT(STATUS) = *READ_STATUS;
}
// read data
COMM_PORT(STATUS) = WRITE_ME;
}