SRAM write protect

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KanedaFr
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SRAM write protect

Post by KanedaFr » Thu Jan 14, 2016 10:59 pm

(extract from another post)
Charles MacDonald wrote:
- on every info I read about SRAM, I never found detail about the D1 (WriteProtect) bit .... Does even one game use it (I mean on the cart, not on the code) to really avoid write error ?
I don't think any cartridges which discretely implement SRAM and the ROM banking at A130F1 support that bit, it's for games (which, maybe only SSF2?) that have a custom chip to handle that.
Did someone find a game which need this writeprotect bit ?
If yes, how is it handled on cart ?

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Re: SRAM write protect

Post by Sik » Fri Jan 15, 2016 6:39 am

Screw that, does anybody know where all the information about that mapper came from in the first place? Because not only the write protect bit is there, also it's stated that there's a limit of 32MB (the page values are 6-bit). That's obviously not reverse engineered because there's only one game using bank switching and that one is 5MB, so that sounds like it came from official documentation but somehow we don't have it right now. (maybe the information came from Snake, as he had access to that stuff?)
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Re: SRAM write protect

Post by TmEE co.(TM) » Fri Jan 15, 2016 2:23 pm

The write protect bit works on the ROM + RAM devcarts.
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Re: SRAM write protect

Post by Charles MacDonald » Fri Jan 15, 2016 6:30 pm

It's in the 32X documentation that's floating around.

Also I noticed Beyond Oasis (and perhaps others?) write to these Sega-defined mapper registers despite not actually having one (I checked a real cart), presumably as the development hardware had it. Since the functionality isn't present in the cart it will not cause any problems.

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Re: SRAM write protect

Post by Charles MacDonald » Sun Feb 14, 2016 1:05 am

I opened a few carts today. I can confirm that at least Phantasy Star IV and Sonic 3 do not implement the write protect bit in either game.
I wonder which other games would be candidates to look at?

Off topic:

My Super Street Fighter II cartridge had a modification compared to db-elec's, there's a 0.1uF ceramic capacitor soldered between pins 8 (/VRES) and 11 (ground) of the 315-5779 custom. The PCB layout is identical, the capacitor is directly soldered to the pins of the chip as some kind of post-assembly fix.

Just for a reference I checked the Sonic 3 memory map relating to it being "locked on" or not, which is detected by using the /VRES pin.

(/VRES high, normal game mode)
000000-1FFFFF : Sonic 3 ROM
200000-3FFFFF : FRAM (at any offset where A10 is high, otherwise that area is unused)

(/VRES low, "locked on")
000000-1FFFFF : Unused (the S&K ROM fits here)
200000-3FFFFF : Writing to /TIME area with D0=0 maps FRAM here, D0=1 maps Sonic 3 ROM

The S&K cartridge grounds /VRES on the lock-on connector.

Monster World IV also uses a FM1208 FRAM like Sonic 3 does.

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Re: SRAM write protect

Post by db-electronics » Fri Feb 19, 2016 7:22 pm

Charles MacDonald wrote:My Super Street Fighter II cartridge had a modification compared to db-elec's, there's a 0.1uF ceramic capacitor soldered between pins 8 (/VRES) and 11 (ground) of the 315-5779 custom. The PCB layout is identical, the capacitor is directly soldered to the pins of the chip as some kind of post-assembly fix.
So essentially it's making the #VRES reset pulse slightly longer - right? (assuming #VRES is weakly pulled up).

Maybe they had batches of 315-5779 where the reset timing requirements were not met...
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