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Z80 NMI
Posted: Tue Dec 09, 2008 12:57 am
by Graz
Does anyone know what generates an NMI on the Z80? According to the schematics I have, it's connected to the VDP (pin 70, labeled /NMI). However, I can't find the Z80's NMI mentioned in any documentation, and none of the ROMs I've looked at have a handler at 66h, suggesting that it can at least be disabled on the VDP end. Have I missed something?
Posted: Tue Dec 09, 2008 3:55 am
by TmEE co.(TM)
NMI is generated only in SMS mode when you ground one address line on cart slot, otherwise NMI never happens.
Posted: Tue Dec 09, 2008 3:58 am
by HardWareMan
TmEE co.(TM) wrote:NMI is generated only in SMS mode when you ground one address line on cart slot, otherwise NMI never happens.
Wich one address line? SMS mode - M3 signal on cartrige slot (B31) on ground?
Posted: Tue Dec 09, 2008 8:40 am
by TmEE co.(TM)
M3 is the B30 signal, and it needs to be grounded for SMS mode, and A23 is the signal used for Pause (in SMS, Pause is connected to Z80 NMI line). In MD mode, NMI never happens.
Posted: Tue Dec 09, 2008 4:53 pm
by Graz
If I understand correctly, on a real SMS the NMI is generated in hardware by the pause button. This button is not present on the genesis, but is on the power base converter. Then, the power base converter grounds M3 to signal SMS compatibility mode.
You say that A23 is used for pause. Does the pause button on the power base converter connect directly to this line? How does that in turn generate the Z80 NMI via the VDP so that the SMS game will pause?
Posted: Tue Dec 09, 2008 6:54 pm
by Eke
the M3 pin is connected to the VDP, I/O chip and to the Bus Arbitrer (the glue chip), this apparently put those three chips in SMS compatibility mode
the Z80 NMI input is connected to the Bus Arbitrer
most probably, when M3 is asserted, as soon as A23 state changes, the bus arbitrer triggers a NMI interrupt on Z80 side
Posted: Wed Dec 10, 2008 12:47 am
by Graz
That's interesting. I wonder if there is any way to programatically generate an NMI from the 68K. Has anyone ever probed the undocumented area above A11200? It makes sense that if Sega were to plan such a feature, that is where the register would be. For example, what happens when a write is performed to A11300?
Posted: Wed Dec 10, 2008 3:32 am
by HardWareMan
TmEE co.(TM) wrote:M3 is the B30 signal, and it needs to be grounded for SMS mode, and A23 is the signal used for Pause (in SMS, Pause is connected to Z80 NMI line). In MD mode, NMI never happens.
Sure, my mistake. It is B30, becouse B31 is !TIME signal.
So, when MD in M3 mode, A23 routed directly to Z80 NMI, or trough some pulse-forming logic? I mean, Z80 NMI signal is edge sensitive signal, and no need to make pulse with normed width.
Posted: Wed Dec 10, 2008 6:48 am
by TmEE co.(TM)
There are some extra components involved in SMS1, I only have SMS2 and its more integrated than SMS1...
I wonder if there actually is something in the undocumented I/O area... I guess things are probably just mirrored there.
The NMI could be useful command exchanges, place your data in Z80 RAM and trigger NMI...
Posted: Wed Dec 10, 2008 5:06 pm
by Graz
Mirroring usually occurs because of incomplete address decoding. As the Genesis only has (documented) registers at A11000, A11100, and A11200, it makes me wonder what, if anything, might be at A11300. If wrapping occurs, there's probably a mirror of A11000 at A11400, leaving a convenient gap at A11300.
I do have a setup to run code on real hardware. Perhaps I'll experiment some if I can find time. The ability to trigger an interrupt from one CPU to the other in either direction could be quite handy.