nukeykt wrote: ↑
Sat Nov 24, 2018 7:36 pm
One FM clock in my code is 6 master clocks. For example in Genesis Plus GX emulator OPN2_Clock is called 1.27(7.67/6) million times per second(for comparison MAME code works at 53.267 KHz). Like real hardware my implementation updates registers within 12 FM ticks. Look carefully to OPN2_DoRegWrite function.
I see, I agree with that approach. However, I have another question.
Are you really implementing the pipeline? For instance, in function OPN2_PhaseCalcIncrement
you perform a lot operations for the data of the current slot, without holding any intermmediate value in a latch. Can that be real? Of course the chip has a lot of parallel things going on that speed up things but it still looks like a lot to be done in a clock cycle.
Then you have the result stored in pg_inc[slot], but data couldn't be actually stored in the same "slot" as it was passing through.
You use pg_inc in the OPN2_PhaseGenerate
but you calculate slot as
My interpretation of this is that the previous function actually had 20 pipeline stages (20 latches) in hardware. Your writing to the same slot you were using as input does not affect accuracy of emulation because that position will not be read until 20 cycles later. So, in general, it looks like you are respecting the pipeline delays but just not writting a function (latch) for each pipeline stage.
Is my interpretation correct?
Another question is about your function OPN2_DoRegWrite
. chip->write_fm_data is read at the beginning of the function (in the if
statement) but it is modified at the end of the function. Are you representing a latch operation in this way? Because the data written at the end will not be read until the next call to the function.