All of these tests I made 1 year ago and even wrote emulator, but then leaved all this job and it is still in unfinished state

Now I'm trying to write an articles about PSG and YM (in Russian), they will fully explain how chips work (info is based on my tests of course) and will consist of some "layers": entry level, detailed description, full description with tests and examples.

Back to DAC. I made such test:

algo 7, all operators are at +1 of sinus, all TL = $7f, freq = 0, so we have silence. Having prevoius knowledge:

- operator's output is -8168..+8168

- each 8 steps of TL are equal to 6 dB (division by 2)

and adjusting separate TL I realized that:

- operators are shifted first, then are summed

- operators are shifted

**arithmetically**(not logically) by 5 bits

- levels -1 and -2 of DAC are the same. I mean that if you change output from -1 to -2 you won't notice difference on oscillogram. I know it's very strange, but it's true.

- AFAIR, there is level +256, and you can get it summing 2 or more operators, you can't reach it using only 1 operator. Calculations:

+8168 asr 5 = +255

-8168 asr 5 = -256

Setting one operator to +255 and adjusting TL of other operator I found that maximum is +256.

So we have 513 levels, but maybe here is how equality of -1 and -2 affects final output and we have only 512 uniqie levels? I don't know.

I need to revive my work on YM.