I know, but how you read sample from M68k memory?TmEE co.(TM) wrote:There is no FIFO on the DAC register
Or your driver "lives" in M68k?
Read directly from M68k bank - not my way.
Because nothing aligned, and it will require many bank switching.
Moderator: BigEvilCorporation
Really? I see 24 there.r57shell wrote: http://nemesis.hacking-cult.org/MegaDri ... exing3.png
I DON'T see 24 clock cycles between them, 23 only.
In English: I recorded Note = 1, Block = 1, Mult = 1. Expected frequency was near 0.05 Hz. One perriod took in average of 5 ones 945,004 + 945,005 = 1,890,009 samples in wave, it is 19,69 seconds. And real frequency is 0.0508 Hz. Channel frequency is 1048576 times more, so it is nearly equal to 53260.75 with high confidence.Считаем шаблон синуса по фазе:
Генерируем частоту Note=00001.
Расстояние между ступенькой вниз и вверх - 945004 семплов
Расстояние между ступенькой вверх и вниз - 945005 семплов
Было измерено на 5 периодах, т.е. погрешность очень низкая.
Т.е. частоту Ямахи можно считать равной 53260.75 с очень низкой погрешностью.
Notice that manual uses 8 Mhz Clock, so frequency will be 55,555.55 Hz and 1s / 55555 Hz = 18 µs exactly.r57shell wrote:I just tired in searching for precise info.
Common formula:But, I think it is not precise. Where it goes from?18 * (1024 - TIMER A) microseconds
Timer A - all 1's -> 18 µs = 0.018 ms
I suppose 18µ goes from 1s / 53267 Hz =
18,773349353258114780257945820114 µs
http://i1.imageban.ru/out/2013/02/27/2e ... 0fad9f.pngGManiac wrote:Really? I see 24 there.
This is cycles between channels. So prime is ok.GManiac wrote: Guys, don't invent nonexistent things. 24 = 6 cycles * 4 operators and 23 is prime number
Intersting info.GManiac wrote: Calculated ideal value is 53693175 / 7 / 24 / 6 = 53267 Hz.
It is VERY close to value above, deviation is 0.01%.
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Ultimate Mortal Kombat 3 (U) ~17278 ~7500 ~6944
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One more timer57shell wrote:http://i1.imageban.ru/out/2013/02/27/2e ... 0fad9f.pngGManiac wrote:Really? I see 24 there.
So how do you think operators are implemented? Do you think it's a solid process which longs 23 cycles for 4 operators? Prime is NOT ok here. Heh. Even if there is additional processing, old processors work only with even numbers of cycles. Z80 and 6502 have quant of 2 cycles, not 1. I think, YM2612 is not exception.r57shell wrote:This is cycles between channels. So prime is ok.GManiac wrote:Guys, don't invent nonexistent things. 24 = 6 cycles * 4 operators and 23 is prime number
I see rising edge of green line on left border of image.GManiac wrote: You don't see the picture to the left, so your 23 cycles are not confident.
Many options: 4*5+3, 1+4*5+2, 2+4*5+1, 4+4*4+3, even 4*1+19GManiac wrote: So how do you think operators are implemented? Do you think it's a solid process which longs 23 cycles for 4 operators? Prime is NOT ok here. Heh.
i would say this is caused by the imprecision of the model 1 dac outputr57shell wrote: How do you explain that pulse width differs? (time when green HIGH)
On left it's 5 cycles, on right it's 6 cycles. Same on this picture.