I finally took sometime to make some tests about the minimum safe write timings for the YM2612 / YM3438 chip.
I made a lot of tests but still I couldn't test every cases and every registers but hopefully that is enough to confirm (or not) data we got from official documents.
I made all my tests using the 68K CPU (I initially tried with the Z80 but it was really too painful honestly) and i assumed there is no extra delay cycle in writing the YM2612 chip from it (to be honest I had no idea but it definitely seems that this is not the case).
I tested both on YM2612 (MD1 VA0) and the ASIC YM3438 (Nomad and MD3 clone) and so far the write timing seems roughly identical between the 2 (contrary to my initial belief) but I still need to do some tests with the key register on YM2612 to confirm that.
I just completed my tests on the YM2612 and I can confirm that timings are identical.
So far here are the timing given in official docs:
- 17 YM cycles (8 Z80 cycles) between writing the address and data
- no wait between writes to addresses $21-$2F
- 83 YM cycles (39 Z80 cycles) between writes to addresses $30-$9E
- 47 YM cycles (22 Z80 cycles) between writes to addresses $A0-$B6
The good news is that I can confirm almost all these numbers
Still there is some minor but important differences in some parts:
- The documentation said 17 cycles between address / data write.
That really seems pessimist and I couldn't got any problems using 12 cycles (5-6 Z80 cycles).
With 10 cycles or less you indeed got some missed or corrupted writes quickly though.
This is interesting to know as it means we can chain 2 fast Z80 writes (7 cycles + 7 cycles) to write a register.
- The documentation said there is no wait for all $2x registers, and so far that is true except for the $28 register (key on/off) !
As i though this register really need some delay between writes otherwise you will got some unwanted results as completely missed writes or even altered envelop phase (!?!) when you chain key operations too quickly on the same channel (note play but quieter than expected).
The minimum delay for safe operation is about 112-116 cycles (52-54 Z80 cycles) which is quite a lot (but I expected even more here). That is more than the 83 cycles required for writing $30-$9E registers.
- The 83 cycles / 47 cycles for $30-$9E / $A0-$B6 registers seems to perfectly
matches what i measured.
There is some quirks about the ASIC YM3438 to be aware of as it makes it behave a bit differently when we read the status and the busy flag in particular :
- unlike the YM2612 the status can only be read on the port #0.
- the busy bit isn't immediately set to 1 when writing register. I dunno how much time it takes exactly to be set but waiting 20 YM cycles after the register write is enough to avoid any problem with that.