25 slots = 25 x 4 EDCLK not MCLK !
Also, I count only 23 slots from the left of the page to HSYNC so this makes 368 Mcycles.
However, you need to understand that timings in hvc.h refer to the video timings observed in the previous thread, they are NOT related to the slot access (as most likely, in the VDP, "events" are not related to access slots but the internal clock) .
Similarly, there are no references to HINT, H Counter or display borders in Nemesis diagrams, just slots positions related to EDCLK and therefore "2 cells" groups are NOT necessarily aligned to rendered pixels as you seem to assume (and they probably aren't if you compare HSYNC timings from both thread).
The "only" thing you need to do is gather informations from both threads, using the only common reference in both ones which is HSYNC timing, to get what you want, quite all the information needed is in there (though I think it still misses HINT & video timings in H32 mode)
Now, from the previous thread :
78 EDCLK = 312 MCLK, this is were hvc.h timings come from.There are 78 EDclk cycles (All Mclk/4) from H-int falling edge to sync pulse falling edge
So, apparently, this *would* mean that HINT is triggered after SC=706, i.e between access slot 176~177.