Megadrive video timings
Posted: Thu Feb 12, 2009 11:04 pm
Taken from a 53.2034MHz MD in NTSC mode running demos from S&K
Vsync, Hsync and Csync are forced low, but not high, only released, the pull-ups slowly drive them high, after a while, so EDclk is in "slow mode" (Mclk/5) for 3 cycles, because the 315-5433 looks at theese signals to produce the EDclk.
/Csync on Yellow;
/YS on Green;
/IPL2 on Purple;
EDclk (after FB7) on Blue (AC coupled, forgot to fix that, but it doesn't change anything at all)
9 lines have shorter hsync pulses and middle pulses of the same length.
A full Hsync pulse is forced low by the VDP N-mosfet and after 64 EDclks (7Mclks/4 + 57Mclks/5) it's released, but because it's not forced high (only pulled), EDclk is still Mclk/5 for 3 cycles while hsync is rising, then the 315-5433 toggles EDclk back to Mclk/4.
Half Hsync pulses are 32 EDclks (3Mclks/4 + 29Mclks/5), same history with the slowly rising edges.
Line 31 (in NTSC) is the first VDP-drawn line.
A close-up on line 254. The color borders are both 26EDclks(Mclk/4).
Errata: Nope, the back border is longer, it's 28EDclks.
The front-porch (hsync released to YS falling) is 64EDclks long (3Mclks/5 + 61Mclks/4)
The back-porch (YS rising to hsync falling) is 18EDclks long (18Mclks/4)
The blanking period is just a sum of everything above + sync period.
Vint is triggered in here. It's 40EDclks (3Mclks/5 + 37Mclks/4) after hsync is released.
The 262nd line, the last one in this pseudo NTSC.
PAL mode coming soon
Vsync, Hsync and Csync are forced low, but not high, only released, the pull-ups slowly drive them high, after a while, so EDclk is in "slow mode" (Mclk/5) for 3 cycles, because the 315-5433 looks at theese signals to produce the EDclk.
/Csync on Yellow;
/YS on Green;
/IPL2 on Purple;
EDclk (after FB7) on Blue (AC coupled, forgot to fix that, but it doesn't change anything at all)
9 lines have shorter hsync pulses and middle pulses of the same length.
A full Hsync pulse is forced low by the VDP N-mosfet and after 64 EDclks (7Mclks/4 + 57Mclks/5) it's released, but because it's not forced high (only pulled), EDclk is still Mclk/5 for 3 cycles while hsync is rising, then the 315-5433 toggles EDclk back to Mclk/4.
Half Hsync pulses are 32 EDclks (3Mclks/4 + 29Mclks/5), same history with the slowly rising edges.
Line 31 (in NTSC) is the first VDP-drawn line.
A close-up on line 254. The color borders are both 26EDclks(Mclk/4).
Errata: Nope, the back border is longer, it's 28EDclks.
The front-porch (hsync released to YS falling) is 64EDclks long (3Mclks/5 + 61Mclks/4)
The back-porch (YS rising to hsync falling) is 18EDclks long (18Mclks/4)
The blanking period is just a sum of everything above + sync period.
Vint is triggered in here. It's 40EDclks (3Mclks/5 + 37Mclks/4) after hsync is released.
The 262nd line, the last one in this pseudo NTSC.
PAL mode coming soon