So i think this come from the delay between h-counter = 0x88 and h-int (corresponding to v-counter increment).
The delay is too long so display is switched off during the current line (so my emulator is blanking the entire line).
not exactly
from the disassembling, DMA occurs once Hcounter has reached 0x88. Hint event has nothing to deal with it, it could have happen at any moment before, display OFF & DMA starts is synchronized with hcount=0x88 in all cases.
what it shows is that at the time display is disabled (which is Hcount=0x88 + DMA register writes length) display should be in Hblank
it also shows that if you add the DMA freezing time (16 bytes in CRAM is approx. 38 cpu cycles), you should still be in Hblank when DMA ends and dispaly is enabled again
so it only tells you that the relation between Hblank period and Hcounter is not correct in the emulator
here's the debugging ouput I got:
Code: Select all
176(86319): VDP HVC read --> 0xb08c (0001ac2c)
176(86335): VDP register 19 write --> 0x10 (0001ac30)
*** LINE 36(86347 / 86340 cycles) ***
177(86347): HINT (OFF) pending (0001ac30)
177(86347): VDP register 20 write --> 0x0 (0001ac32)
177(86347): VDP register 21 write --> 0xc2 (0001ac32)
177(86367): VDP register 22 write --> 0x82 (0001ac34)
177(86367): VDP register 23 write --> 0x7f (0001ac34)
177(86387): VDP register 1 write --> 0x34 (0001ac36)
177(86387): VINT enabled, DISPLAY OFF (0001ac36)
177(86387): redraw line (0001ac36)
177(86399): DMA type 1 --> 180 bytes (16 bytes left) (0001ac38)
177(86437): DMA freeze 38 cycles (0001ac38)
177(86437): VDP register 1 write --> 0x64 (0001ac38)
177(86437): VINT enabled, DISPLAY ON (0001ac38)
177(86437): redraw line (0001ac38)
177(86683): VDP HVC read --> 0xb156 (0001ac2c)
177(86701): VDP HVC read --> 0xb15e (0001ac2c)
177(86719): VDP HVC read --> 0xb166 (0001ac2c)
177(86737): VDP HVC read --> 0xb16d (0001ac2c)
177(86755): VDP HVC read --> 0xb175 (0001ac2c)
177(86773): VDP HVC read --> 0xb17d (0001ac2c)
177(86791): VDP HVC read --> 0xb185 (0001ac2c)
177(86809): VDP HVC read --> 0xb18d (0001ac2c)
177(86825): VDP register 19 write --> 0x10 (0001ac30)
177(86837): VDP register 20 write --> 0x0 (0001ac32)
177(86837): VDP register 21 write --> 0xc2 (0001ac32)
177(86857): VDP register 22 write --> 0x82 (0001ac34)
177(86857): VDP register 23 write --> 0x7f (0001ac34)
*** LINE 36 (86877 / 86864 cycles) ***
178(86877): VDP register 1 write --> 0x34 (0001ac36)
178(86877): VINT enabled, DISPLAY OFF (0001ac36)
178(86877): redraw line (0001ac36)
178(86889): DMA type 1 --> 194 bytes (16 bytes left) (0001ac38)
178(86927): DMA freeze 38 cycles (0001ac38)
178(86927): VDP register 1 write --> 0x64 (0001ac38)
178(86927): VINT enabled, DISPLAY ON (0001ac38)
the game does not use Hint, only Hcounter to know when Hblank has started so it can trigger a short display OFF/DMA operation between 2 lines
here's the debugging output with line starting at 0xA7
Code: Select all
*** LINE 39 (79068 / 79056 cycles) ***
162(79068): VDP register 1 write --> 0x34 (0001ac36)
162(79068): VINT enabled, DISPLAY OFF (0001ac36)
162(79068): redraw line (0001ac36)
162(79080): DMA type 1 --> 194 bytes (16 bytes left) (0001ac38)
162(79118): DMA freeze 38 cycles (0001ac38)
162(79118): VDP register 1 write --> 0x64 (0001ac38)
162(79118): VINT enabled, DISPLAY ON (0001ac38)
162(79118): redraw line (0001ac38)
162(79364): VDP HVC read --> 0xa259 (0001ac2c)
162(79382): VDP HVC read --> 0xa260 (0001ac2c)
162(79400): VDP HVC read --> 0xa268 (0001ac2c)
162(79418): VDP HVC read --> 0xa270 (0001ac2c)
162(79436): VDP HVC read --> 0xa278 (0001ac2c)
162(79454): VDP HVC read --> 0xa280 (0001ac2c)
162(79472): VDP HVC read --> 0xa287 (0001ac2c)
162(79490): VDP HVC read --> 0xa28f (0001ac2c)
162(79506): VDP register 19 write --> 0x10 (0001ac30)
*** LINE 39:(79518 / 79508 cycles) ***
163(79518): HINT (OFF) pending (0001ac30)
163(79518): VDP register 20 write --> 0x0 (0001ac32)
163(79518): VDP register 21 write --> 0xc2 (0001ac32)
163(79538): VDP register 22 write --> 0x82 (0001ac34)
163(79538): VDP register 23 write --> 0x7f (0001ac34)
163(79558): VDP register 1 write --> 0x34 (0001ac36)
163(79558): VINT enabled, DISPLAY OFF (0001ac36)
163(79558): redraw line (0001ac36)
163(79570): DMA type 1 --> 178 bytes (16 bytes left) (0001ac38)
163(79608): DMA freeze 38 cycles (0001ac38)
163(79608): VDP register 1 write --> 0x64 (0001ac38)
163(79608): VINT enabled, DISPLAY ON (0001ac38)
163(79608): redraw line (0001ac38)
163(79854): VDP HVC read --> 0xa35a (0001ac2c)
163(79872): VDP HVC read --> 0xa361 (0001ac2c)
163(79890): VDP HVC read --> 0xa369 (0001ac2c)
163(79908): VDP HVC read --> 0xa371 (0001ac2c)
163(79926): VDP HVC read --> 0xa379 (0001ac2c)
163(79944): VDP HVC read --> 0xa380 (0001ac2c)
163(79962): VDP HVC read --> 0xa388 (0001ac2c)
163(79978): VDP register 19 write --> 0x10 (0001ac30)
163(79990): VDP register 20 write --> 0x0 (0001ac32)
163(79990): VDP register 21 write --> 0xc2 (0001ac32)
163(80010): VDP register 22 write --> 0x82 (0001ac34)
163(80010): VDP register 23 write --> 0x7f (0001ac34)
163(80030): VDP register 1 write --> 0x34 (0001ac36)
163(80030): VINT enabled, DISPLAY OFF (0001ac36)
163(80030): NOT redraw line (0001ac36)
*** LINE 39 (80042 / 80032 cycles) ***
164(80042): DMA type 1 --> 200 bytes (16 bytes left) (0001ac38)
164(80080): DMA freeze 38 cycles (0001ac38)
164(80080): VDP register 1 write --> 0x64 (0001ac38)
164(80080): VINT enabled, DISPLAY ON (0001ac38)
164(80080): redraw line (0001ac38)
What happen is that the routine is triggered earlier and display OFF would is sometime triggered at the end of the previous emulated line... if I choose to redraw the
entire line in such case, it is indeed incorrect because the active line has eventually already finish its rendering and is already in hblank.
As you can see, if the last values being read would have been 0x87 instead of 0x88, there would have been an additional read and the display would have been switched OFF on the next line like before.
The conclusion is that it is not only a matter of correct Hcounter, it is also a matter on HOW and WHEN you are rendering the line. 0xA7 might be a correct value on the real thing but on a line-based emulator, the timings probably need to be more optimistic and leave some room for approximations like that...
mickagame wrote:
But I think Eke you're right if display is switched on/off outside the display area this will take effect on the next line.
So i consider this timings are ok.
No, I didn't say that, I said the contrary: most probably, enabling/disabling the display can have immediate (mid-line) effect
And as I showed above, you can NOT tell timings are right or wrong just because they don't work in emulators... it can be a lot of other things that would impact timings and that are not emulated or only partially emulated.
What you CAN say is that
in your emulator which starts the line with hint event, Hcounter apparently should began at 0xA5... but this does not mean that on the real thing, Hint occurs necessarely at Hcount=0xa5... see the difference ?
An alternate way to do would be to have the exact same piece of code (for example, a loop reading Hcounter in Hint routine like Jorge Nuno did) running on both emulator / real hardware and then adjusting your Hcounter table offset to match real hardware... because at the end, what matters in our case is to match real hardware output, even if the emulation is not exactly accurate
The purpose of the topic however is to know the VDP exact timings which can unfortunately only be speculated by tests with emulators...