Megadrive video timings

For anything related to VDP (plane, color, sprite, tiles)

Moderators: BigEvilCorporation, Mask of Destiny

Post Reply
Jorge Nuno
Very interested
Posts: 374
Joined: Mon Jun 11, 2007 3:09 am
Location: Azeitão, PT

Megadrive video timings

Post by Jorge Nuno » Thu Feb 12, 2009 11:04 pm

Taken from a 53.2034MHz MD in NTSC mode running demos from S&K

Vsync, Hsync and Csync are forced low, but not high, only released, the pull-ups slowly drive them high, after a while, so EDclk is in "slow mode" (Mclk/5) for 3 cycles, because the 315-5433 looks at theese signals to produce the EDclk.

/Csync on Yellow;
/YS on Green;
/IPL2 on Purple;
EDclk (after FB7) on Blue (AC coupled, forgot to fix that, but it doesn't change anything at all)
Image
9 lines have shorter hsync pulses and middle pulses of the same length.

A full Hsync pulse is forced low by the VDP N-mosfet and after 64 EDclks (7Mclks/4 + 57Mclks/5) it's released, but because it's not forced high (only pulled), EDclk is still Mclk/5 for 3 cycles while hsync is rising, then the 315-5433 toggles EDclk back to Mclk/4.

Half Hsync pulses are 32 EDclks (3Mclks/4 + 29Mclks/5), same history with the slowly rising edges.


Image
Line 31 (in NTSC) is the first VDP-drawn line.


Image
A close-up on line 254. The color borders are both 26EDclks(Mclk/4).
Errata: Nope, the back border is longer, it's 28EDclks.

The front-porch (hsync released to YS falling) is 64EDclks long (3Mclks/5 + 61Mclks/4)
The back-porch (YS rising to hsync falling) is 18EDclks long (18Mclks/4)

The blanking period is just a sum of everything above + sync period.



Image
Vint is triggered in here. It's 40EDclks (3Mclks/5 + 37Mclks/4) after hsync is released.


Image
The 262nd line, the last one in this pseudo NTSC.


PAL mode coming soon :lol: 8)
Last edited by Jorge Nuno on Sat Feb 14, 2009 12:05 am, edited 1 time in total.

Stef
Very interested
Posts: 2976
Joined: Thu Nov 30, 2006 9:46 pm
Location: France - Sevres
Contact:

Post by Stef » Thu Feb 12, 2009 11:16 pm

Awesome !
It would be nice to resume all these numbers in a table as soon PAL is done.
This time we have exact numbers on an oscillo to prove them :)

Snake
Very interested
Posts: 203
Joined: Sat Sep 13, 2008 1:01 am

Post by Snake » Thu Feb 12, 2009 11:25 pm

Matches my info :)

There's some other VDP stuff you could test, but that probably requires a custom test ROM. I'll PM later :)

Jorge Nuno
Very interested
Posts: 374
Joined: Mon Jun 11, 2007 3:09 am
Location: Azeitão, PT

Post by Jorge Nuno » Thu Feb 12, 2009 11:29 pm

Snake don't bother yet, because my programmable cart isn't ready (read: it doesn't work, and I don't know why)

Snake
Very interested
Posts: 203
Joined: Sat Sep 13, 2008 1:01 am

Post by Snake » Thu Feb 12, 2009 11:48 pm

Jorge Nuno wrote:Snake don't bother yet, because my programmable cart isn't ready (read: it doesn't work, and I don't know why)
Ah, ok. For future reference, when it IS ready, how big a ROM will it support?

Jorge Nuno
Very interested
Posts: 374
Joined: Mon Jun 11, 2007 3:09 am
Location: Azeitão, PT

Post by Jorge Nuno » Thu Feb 12, 2009 11:53 pm

512 kByte (yup :oops: :lol: ). It's my first one... I'll try to get it working in the following days... or weeks :x .

BTW what do you want to test?

ob1
Very interested
Posts: 407
Joined: Wed Dec 06, 2006 9:01 am
Location: Aix-en-Provence, France

Post by ob1 » Fri Feb 13, 2009 8:44 am

Great. Indeed. Thank you Jorge !!!

Eke
Very interested
Posts: 856
Joined: Wed Feb 28, 2007 2:57 pm
Contact:

Post by Eke » Fri Feb 13, 2009 9:22 am

thank you very much Jorge ...

some stuff that I still would like to know eventually:

1/ Hint triggering regarding to hsync : check IPL2 and IPL1 with a game using the horizontal interrupt
2/ does Vint remains pending and how long if not acknowledged by CPU: check IPL1 from line 224 with interrupts disabled on 68k, would require a test ROM
3/ same for Hint, check IPL2 with Vint disabled on the VDP and interrupts disabled on 68k, would require a test ROM
4/ measure IPL1/IPL2 when both Hint and Vint are set on line 224
5/ same measures in H32 mode only ... and in PAL mode ;-)

but thanks again, those are already very valuable informations to me :)

so, if I didn't make any mistake with calculations, this would mean, that in H40 mode:

- Hblank area is (86/2) + (60/2) = 73 "pixels" count (43 "H40" pixels and 30 "H32" pixels)
--> (43*8 + 30*10)/7 = 92 CPU cycles

- Overscan area is 2 x 13 = 26 "H40" pixels
--> 26*8/7 = approx. 30 CPU cycles

- Full line width is 320 + 73 + 26 = 419 pixels count (389 "H40" pixels and 30 "H32" pixels)
--> (389*8 + 30*10)/7 = 3412/7 = approx. 487.5 CPU cycles


Could you measure the two borders more precisely, It seems one is wider than the other (btw, in H32 mode, it is supposed to be 15 +13 pixels, maybe it's still the case here)

also, still according to Charles McDonald, Hcounter range is 00-B6;E4-FFh which is actually 421 or 422 dot counts, which would tends to confirm the border area is a little "wider"
Last edited by Eke on Fri Feb 13, 2009 2:40 pm, edited 4 times in total.

mickagame
Very interested
Posts: 212
Joined: Sat Jun 07, 2008 7:37 am

Post by mickagame » Fri Feb 13, 2009 9:26 am

Very interesting infos Jorge !!!

I would be interested by these infos too. wonderful work :D

Jorge Nuno
Very interested
Posts: 374
Joined: Mon Jun 11, 2007 3:09 am
Location: Azeitão, PT

Post by Jorge Nuno » Fri Feb 13, 2009 1:42 pm

Back border is wrong :( ; it's 28EDclks (28Mclks/4) while the front border is 26EDclks (26Mclks/4), which means that a full line is 420 pixels, though almost all of the pixels of the sync portion are larger (EDclk is slower) than the active ones.

Eke
Very interested
Posts: 856
Joined: Wed Feb 28, 2007 2:57 pm
Contact:

Post by Eke » Fri Feb 13, 2009 2:36 pm

thanks,

so, again:

- Hblank area is (86/2) + (60/2) = 73 "pixels" count (43 "H40" pixels and 30 "H32" pixels)
--> (43*8 + 30*10)/7 = 92 CPU cycles (644 Mcycles)

- Overscan area is 14 +13 = 27 "H40" pixels
--> 27*8/7 = approx. 31 CPU cycles (216 Mcycles)

- Full line width is 320 + 73 + 27 = 420 pixels count (390 "H40" pixels and 30 "H32" pixels)
--> (390*8 + 30*10)/7 = 3420/7 = approx. 488.5 CPU cycles

This also means a "line" is 3420 Mcycles, active width being 2560 Mcycles and blanking being 860 cycles, which is similar to Charles's tests in SMS mode (framerate is 53693175/3420/262 = 59.92 fps in both modes) and values in 32x documentation (as posted here)


I love when everything starts to fit correctly :D
Last edited by Eke on Fri Feb 20, 2009 3:27 pm, edited 5 times in total.

Jorge Nuno
Very interested
Posts: 374
Joined: Mon Jun 11, 2007 3:09 am
Location: Azeitão, PT

Post by Jorge Nuno » Fri Feb 13, 2009 3:03 pm

Yup. The math seems to be correct, I've made them myself too.

S1 and S2 have HINT in water levels;
S2 has a 256 pixel display in the special stages and an interlace mode 2 in 2players vs;
Ecco2 EU has a 240 line display in some levels and HINTs in 3D stages.
Last edited by Jorge Nuno on Sat Feb 14, 2009 12:14 am, edited 1 time in total.

Snake
Very interested
Posts: 203
Joined: Sat Sep 13, 2008 1:01 am

Post by Snake » Sat Feb 14, 2009 12:13 am

Eke wrote:(43 "H40" pixels and 30 "H32" pixels)
Hmm, I'd like to see this stuff specifically tested in H32 mode. It seems to me the timing is a little different, but you'd really need a scope to tell for sure. It's probably not different enough to be important, but still ;)

The stuff I wanted testing isn't really important either, more just 'out of interest', and has to do with vdp activity during the vblank area.

Eke
Very interested
Posts: 856
Joined: Wed Feb 28, 2007 2:57 pm
Contact:

Post by Eke » Mon Feb 16, 2009 10:46 am

(not so) surprisingly, this somehow matches the TMS9918 documentation:

Image

you can see that:

1/ right border + right blank is still 23 pixels count: however, this is meant to be 15 +8 pixels, not 14 +9 pixels as you measured...

2/ left border is still 13 pixels count


a few more maths about Hint: according to a sega bulletin, Hint is triggered 14.7 us before Vint which is approx. 790 Mcycles

this would mean Hint is approx. triggered 790 - (3*5 + 37*4 + 7*4 + 57*5 + 18*4 + 28*4) = 130 Mcycles before HBLANK (start of the right border)

also note that if the right border is 15 pixels (instead of 14) and the right blank is 8 pixels (instead of 9), this would mean HINT occurs approx. 250 Mcycles before the end of the right border

and 250 Mcycles = approx. 36 CPU cycles which is also a value used in offcial docs ;-)
Last edited by Eke on Mon Feb 16, 2009 3:25 pm, edited 1 time in total.

mickagame
Very interested
Posts: 212
Joined: Sat Jun 07, 2008 7:37 am

Post by mickagame » Mon Feb 16, 2009 12:16 pm

So for exact timings you have something like this :

H-INT + 000 Mclks : H-Sync
H-INT + 130 Mclks : HBlank Start
H-INT + 252 Mclks : Registers fetched, render line
H-INT + 308 Mclks : 68k executes first interrupt instruction if interrupt occured.

Do you agree?

Post Reply