HBlank Timings

mickagame · Post by **mickagame** » Sun Mar 08, 2009 11:22 pm

I made this schema to detail VDP timings in H40 mode :

- 320 "H40 dots" (H40DCLKS) (Active Display)
- 26,5 (correct to 26) "H40 dots" (H40DCLKS) (Back border, Back porch, Start HSync)
- 30 "H32 dots" (H32DCLKS) (End HSync, Start front porch)
- 43,5 (correct to 44) "H40 dots" (H40DCLKS) (End front porch, Front border)

I supposed HBlank flag period begin with E5 value as Eke suggested.

corrected after eke post :

Code: Select all


|       | .  |H40| . |     .      |
|       | .  |H40| . |     .      |
|       |0x9E|H40|316|DISPLAY     |
|       |--------------------------- H-INT              -
|       |0x9E|H40|317|DISPLAY     |                     |
| line  | .  |H40| . |DISPLAY     |                     |                   
| n - 1 | .  |H40| . |DISPLAY     |                     | 128 MCLKS
|       |0xA5|H40|330|DISPLAY     |                     |
|       |0xA5|H40|331|DISPLAY     |                     |
|       |0xA6|H40|332|DISPLAY     |                     |
|-------|--------------------------- |V-COUNTER INC     -                    -
|       |0xA6|H40|333|RIGHT BORDER|  |H-BLANK START     |                    |
|       | .  |H40| . |     .      |                     |                    |
|       | .  |H40| . |     .      |                     |                    |
|       |0xAD|H40|346|RIGHT BORDER|                     |                    |
|       |0xAD|H40|347|RIGHT BORDER|                     |                    |
|       |0xAE|H40|348|BACK PORCH  |                     |                    |
|       |0xAE|H40|349|BACK PORCH  |                     |                    |
|       | .  |H40| . |     .      |                     |                    |
|       | .  |H40| . |     .      |                     |                    |
|       |0xB2|H40|356|BACK PORCH  |                     | 278 MCLK           |
|       |0xB2|H40|357|HSYNC       |                     | -> 26 *  8 MCLKS   |
|       |0xB3|H40|358|HSYNC       |                     | ->  7 * 10 MCLKS   |
|       |0xB3|H32|359|HSYNC       |                     |                    |
|       |0xB4|H32|360|HSYNC       |                     |                    |
|       | .  |H32| . |     .      |                     |                    |
|       | .  |H32| . |     .      |                     |                    |
|       |0xB6|H32|364|HSYNC       |                     |                    | 
|       |0xB6|H32|365|HSYNC       |                     |                    | 860 MCLKS
|       |--------------------------- HBLANK FLAG START  -                    |   
|       |0xE5|H32|366|HSYNC       |                     |                    |
|       |0xE5|H32|367|HSYNC       |                     |                    |
|       | .  |H32| . |     .      |                     |                    |
| line  | .  |H32| . |     .      |                     |                    |
|   n   |0xEE|H32|385|HSYNC       |                     |                    |
|       |0xEF|H32|386|FRONT PORCH |                     |                    |
|       |0xEF|H32|387|FRONT PORCH |                     | 582 MCLKS          |
|       |0xF0|H32|388|FRONT PORCH |                     | -> 23 * 10 MCLKS   |
|       |0xF0|H40|389|FRONT PORCH |                     | -> 44 *  8 MCLKS   |
|       | .  |H40| . |     .      |                     |                    |
|       | .  |H40| . |     .      |                     |                    |
|       |0xFF|H40|418|FRONT PORCH |                     |                    |
|       |0xFF|H40|419|FRONT PORCH |                     |                    |
|       |0x00|H40|000|LEFT BORDER |                     |                    |
|       |0x00|H40|001|LEFT BORDER |                     |                    |
|       | .  |H40| . |     .      |                     |                    |
|       | .  |H40| . |     .      |                     |                    |
|       |0x06|H40|012|LEFT BORDER |                     |                    |
|       |--------------------------- |H-BLANK-END       -                    -
|       |0x06|H40|013|DISPLAY     |  |HBLANK FLAG END                     
|       |0x07|H40|014|DISPLAY     |
|       |0x07|H40|015|DISPLAY     |
|       | .  |H40| . |     .      |
|       | .  |H40| . |     .      |

Eke · Post by **Eke** » Mon Mar 09, 2009 9:01 am

I've done the same thing as you but got different values:

-left border is 13 pixels so it should end with pixel 12, not 13

- HBLANK as we have defined it previously include the two borders (you didn't in your schema): it starts 320 pixels after the end of left border so it starts with pixel 333 (0xA6), not 0xA0. This is also probably where Vcounter is incremented (seems logical)

- Hint occurs 16 pixels before HBLANK start so it occurs at pixel 317 (0x9E)

Last point: with previous observations, we can tell VINT occurs at Hcount=0xF4 (which is the same as INT occurence in SMS mode)

mickagame · Post by **mickagame** » Mon Mar 09, 2009 10:05 am

Everything seems to feet correctly.
I corrected the schema.

Eke · Post by **Eke** » Mon Mar 09, 2009 10:19 am

There are still some errors with "H32 pixels" and MCLK during HBLANK
Check the other post for the exact repartition of "H32-like" and "H40-like" during HBLANK.

HSYNC is bounded by the front porch and the back porch:
right border > back porch -> HSYNC -> front porch -> left border

only HSYNC and front porch have some "H32" pixels

mickagame · Post by **mickagame** » Mon Mar 09, 2009 10:54 am

I forgot to correct them.
Now is ok.

For V-INT interrupt, i calcul it happens juste before H-COUNTER = 0xFA.

I explain :

- According to Jorge Nuno Delay between H-INT and V-INT is 788 MCLKS.
- According to my schema, delay between H-INT and H-BLANK END is 988 MCLKS
- So V-INT happens 200 MCLKS before H-BLANK END
- 200/8 = 25 "H40 pixels"
- There are 13 pixels of left border so 25 - 13 = 12 pixels
- 419 -12 = 407
- So V-int occurs just after h-counter = 407 = 0xF9 -> just before H-Counter = 0xFA

Eke · Post by **Eke** » Mon Mar 09, 2009 2:45 pm

Here's what I got

I made the right borders being 15 pixels like in H32 mode, but it's not so important

Here is the same for H32 mode, missing HINT/VINT occurences:

mickagame · Post by **mickagame** » Mon Mar 09, 2009 4:35 pm

Another question :
Gorge in his post says that line 31 in NTSC is the first drawn line.
There is a relation between vcounter value?

Eke · Post by **Eke** » Mon Mar 09, 2009 4:47 pm

There is no way to know ...

according to Charles document again:

NTSC, 256x224
-------------

Lines Description

224 Active display
8 Bottom border
3 Bottom blanking
3 Vertical blanking
13 Top blanking
11 Top border

V counter values
00-EA, E5-FF

If you look at the way he tested it, his "last line" you occurs 8 lines after the line where VINT occurs (line 224)

Well, we know bottom border is indeed 8 lines, so you can figure that the "first line" is in fact line 232 (starts of the bottom blanking)

If you take the rest: 3+3+13+11 = 30 lines

The first active line probably starts with Vcounter= 0 (VBLANK flag is set when VCOUNT=0xE0) but there is no way to know on which line the VDP really starts... this is not really important from an emulation point of view though.

mickagame · Post by **mickagame** » Mon Mar 09, 2009 4:55 pm

Yes.
I will compare my schemas with yours.

Thank you for all.

mickagame · Post by **mickagame** » Mon Mar 09, 2009 6:26 pm

So interrupt occurs at H_counter = 0xF9.
Our schemas are exactly the same

mickagame · Post by **mickagame** » Tue Mar 10, 2009 12:39 pm

I set this timings in my emulator.
The delay between H-INT and HBLANK=0 give me problem with the blue bar of sonic 2.

I already had this problem before.
extract of my previous response to this topic :

H-INT : 0
HBlankStart = H-INT + 130 MClks
HBlankEnd = H-INT + 130 MClks + 860 Mclks

So the delay between H-INT and HBlankEnd is 990 MClks
The 68K needs 44 Clks (308 Mclks) to fetch registers before executing first instruction of the interrupt.

So the 68k can execute 682 MClks before the end of HBlank.

The problem is :
Before testing HBlank Flag in status register, there are others instructions at start at interrupt processus.
With my timings, the 68k can execute this instructions and test the hblank flag during this 682 MClks (before end of hblank) so the display is switch Off during this Hblank juste after the H-Int (line 107).

That's not normal because line 107 don't have to be displayed off !!!
I think that in real hardware, when the 68k do the first test of hblank flag, the first hblank period must be ended, so the display will be switched off next line.

Eke · Post by **Eke** » Tue Mar 10, 2009 1:53 pm

Then maybe those timings are wrong or there is something more involved, who knows ?
This is the downside of speculating without doing any test, I told you

It would require someone willing to test exactly when the HBLANK flag is set/cleared regarding to the HINT occurence...

EDIt: I modified my schema

for example, something like this could fit as well (considering there was some latency while reading VDP status and HVcounter, we don't really know how this has been tested)

mickagame · Post by **mickagame** » Tue Mar 10, 2009 2:31 pm

Have you the possibility eke to test this hblank flag timings (h-int + 406 -> hblank flag = 1, h-int + 988 -> hblank flag = 0) in genesis plus to see if you have the same problem with the first line of blue bar?

Eke · Post by **Eke** » Tue Mar 10, 2009 2:43 pm

here's what I got with such timings, the last line of the separation bar is obviously wrongly displayed

with current timings (Hblank flag is cleared at hint + 860), everything is fine

mickagame · Post by **mickagame** » Tue Mar 10, 2009 3:09 pm

So with hblank cleared at H-int + 988 the game doesn't display correctly?
The only difference is that for me this is the first bar that is wrongly displayed.

Here is the reason :

Code: Select all

ROM:00000F54 HInt:                                   ; DATA XREF: ROM:00000070o          Start       Length
ROM:00000F54                 tst.w   ($FFFFF644).w                                         309         84
ROM:00000F58                 beq.w   locret_FFE                                            393         84
ROM:00000F5C                 tst.w   ($FFFFFFD8).w                                         477         84
ROM:00000F60                 beq.w   loc_1000                                              561         84
ROM:00000F64                 move.w  #0,($FFFFF644).w                                      645         112
ROM:00000F6A                 move.l  a5,-(sp)                                              757         84
ROM:00000F6C                 move.l  d0,-(sp)                                              841         84
ROM:00000F6E
ROM:00000F6E loc_F6E:                                ; CODE XREF: HInt+24j
ROM:00000F6E                 move.w  (VDP_Control).l,d0                                    925     
ROM:00000F74                 andi.w  #4,d0
ROM:00000F78                 beq.s   loc_F6E
ROM:00000F7A                 move.w  ($FFFFF60C).w,d0
ROM:00000F7E                 andi.b  #$BF,d0
ROM:00000F82                 move.w  d0,(VDP_Control).l
ROM:00000F88                 move.w  #$8228,(VDP_Control).l
ROM:00000F90                 move.l  #$40000010,(VDP_Control).l
ROM:00000F9A                 move.l  ($FFFFEEEC).w,(VDP_Data).l
ROM:00000FA2                 move.w  #$100,(Z80BusReq).l ; D8 ( W)   0: BUSREQ CANCEL
ROM:00000FA2                                         ;           1: BUSREQ REQUEST
ROM:00000FA2                                         ;    ( R)   0: CPU FUNCTION STOP ACCESSIBLE
ROM:00000FA2                                         ;           1: FUNCTIONING
ROM:00000FAA

As you ca see, at time = h-int + 925 the hblank flag is tested.
So if h-blank flag is 1, the display is switched off (line 107) -> it's wrong.

With time = h-int +860, it must be correct, but i will do test.