VDP registers timings

TmEE co.(TM) · Post by **TmEE co.(TM)** » Wed Nov 17, 2010 9:37 am

The 2 pixel colors are different, I need to see if I can get a good shot from a capture card, and I'll try Mega Turrican too, it does same in the title screen, at least I recall it doing so...

The data read from VRAM is shown 16 pixels later on the screen (I did some visual tests with RGB lines and probing random stuff in the MD). Sprite processing begins 304th pixel on visible line, and 8 screen pixels = 32 spire pixels read out from VRAM. I need to redo these things...

Charles MacDonald · Post by **Charles MacDonald** » Thu Nov 18, 2010 2:43 am

Eke wrote: I guess we know where these values come from now

Wow, great work!

How do we know how many pixels there are per line in H40 mode?

To my understanding, the master clock is 53.693175 MHz, which gives some dividers

mclk/15 = 3.579545 MHz, Z80 clock
mclk/7 = 7.67 MHz, 68K clock
mclk/10 = 5.36 MHz, H32/Mode 4 pixel clock (matches SMS exactly)
mclk/8 - 6.711 MHz, H40 pixel clock

Now to figure out the dots per line, we know there are 342 dots exactly in Mode 4 (by Sega's docs) so 342 x 10 = 3420 mclks per line, and 3420/8 = 427.5 pixels per line in H40 mode which I guess end up being 426 or 428. But maybe that's wrong since it's too far from 420.

But that's just an assumption, it could be a number other than 3420 mclks per line in H40 mode.

Eke · Post by **Eke** » Thu Nov 18, 2010 8:08 am

Charles MacDonald wrote:
How do we know how many pixels there are per line in H40 mode?

check that thread
viewtopic.php?t=519

Jorge Nuno has observed that the pixel clock is derivated from EDCLK in H40 mode (dot clock = EDCLK/2). In H32 mode, dot clock is generated by the VDP internally and is fixed to MCLK/10.

EDCLK is generated by the main ASIC (bus arbiter, not VDP) and is MCLK/5 during HSYNC (/HSYNC low), MCLK/4 otherwise. To be exact (HardwareMan did more detailled measures later), during HSYNC, EDCLK is oscillating between MCLK/5 and MCLK/4 (15 cycles @MCLK/5 followed by 2 cycles @MCLK/4).

The result is exactly 420 pixels per line. Interestingly, this confirms what is written in the 32x doc posted in the very first page of this thread. This is also confirmed by Nemesis tests on HCounter values range.

There are 3420 MCycles on a line, 2560 MCycles for active display and 860 for "blanking", in both modes.

Charles MacDonald · Post by **Charles MacDonald** » Fri Nov 19, 2010 5:00 am

Eke wrote:EDCLK is oscillating between MCLK/5 and MCLK/4 (15 cycles @MCLK/5 followed by 2 cycles @MCLK/4).

Ah, this is great to know. It explains why the video timings are different for System 18 / System C2.

I feel certain the SEL1 pin tells the VDP to input an external EDCLK signal, or internally generate EDCLK. The Genesis and MegaTech systems both have the ASIC and SEL1 grounded, so they accept the external clock.

System 18 and C2 have no ASIC and SEL1 tied to +5V, and their video timings are not the same as a result. I wonder if the lack of a faster clock rate during HSYNC impacts any limits of sprite processing?

I'll try to do some tests on these boards to confirm it, but it seems clear now.

Jorge Nuno · Post by **Jorge Nuno** » Fri Nov 19, 2010 11:18 am

Nope, SEL1 is about the 68000 clock. <- This is how I got the synchronous overclock
"SEL1 I, Switches Clk1 direction: 0 = Mclk/7, 1 = I(nput);"
[ http://wiki.megadrive.org/index.php?tit ... :VDPpinout ]

The Pixel clock characteristics (and display mode) is got from the settings of reg C:
http://wiki.megadrive.org/index.php?tit ... s_Addendum