Understanding VDP

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mickagame
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Understanding VDP

Post by mickagame » Sun May 24, 2015 7:30 pm

Reading the documentation of Nemesis I understand that VDP access to VRAM are divided in slots. There are slots called "external slots access".

When performing DMA The DMA use these slots to access VRAM?
There is a link between these slots and the VDP FIFO?

I work actually on a VDP core at slot level and i would like understanding exactly how it works internally to have a good code design.

Thanks for your help.

Mask of Destiny
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Post by Mask of Destiny » Sun May 24, 2015 8:21 pm

So generally speaking, everything the VDP does is organized around a unit of 4 cycles of its current clock (MCLK/4 or MCLK/5 depending on the video mode with some switching between the two during hsync for H40 mode). In 4 cycles, the VDP can either read 4 consecutive bytes from the serial port, read or write a single byte using the parallel port or do a refresh operation. Any 4 cycle period (a slot in other words) that is not be used by the VDP for rendering or refresh is available for servicing external requests from the 68K. These are called an external slot in Nemesis' documentation.

Normal writes and 68K -> VRAM DMA transfers go through the FIFO. DMA fills don't go through the FIFO, but use the FIFO as a value source for the fill. Additionally, the write that triggers the fill goes through as a normal write. DMA copies do not interact with the FIFO at all, but do use the same external slots as other accesses.

mickagame
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Post by mickagame » Sun May 24, 2015 9:32 pm

Thanks for this informations !

I would need more details about how the FIFO is filled.

For example when i write data to VRAM :
1) Data is writed to data port
2) The FIFO is immediately written with this data?
3) Next external slot the VDP take the data from FIFO and write to VRAM

If my step 2) is correct what happen if i write another adress before the external access slot occurs? My data will be written to the new adress?

This example will help me to understand internal design of the chip :-)

Mask of Destiny
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Post by Mask of Destiny » Sun May 24, 2015 9:58 pm

mickagame wrote: 2) The FIFO is immediately written with this data?
3) Next external slot the VDP take the data from FIFO and write to VRAM
My investigations suggest there is a latency of 2 or 3 slots between when a value is read from the 68K's bus to when it can be written to VRAM. It's not clear if this is on the entry to the FIFO or exit.
mickagame wrote: If my step 2) is correct what happen if i write another adress before the external access slot occurs? My data will be written to the new adress?
An entry in the FIFO not only contains the word to be written, but a copy of the internal address register and cd register from the time when the write was added to the FIFO.

mickagame
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Post by mickagame » Mon May 25, 2015 6:09 am

Ok that's more clear :-)
I will try to look in exodus see how nemesis implements this.
Thank u !

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HardWareMan
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Post by HardWareMan » Mon May 25, 2015 6:44 am

I can do more: sniff with logic analyzer how exactly value from M68K bus goes through VDP to VRAM, if you want. Feel free ask, but first make some test ROM for it.

mickagame
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Post by mickagame » Mon May 25, 2015 9:42 am

Thanks for your help if i need i will ask u :-)

If i read VRAM from 68K bus and that FIFO is not empty
=> The read isn't performed until the FIFO is empty.

So the DTACK signal from 68k bus remain high until the data become available (so the 68K is locked)? Or there's another mecanism involved?

Mask of Destiny
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Post by Mask of Destiny » Mon May 25, 2015 6:00 pm

So I haven't had a chance to confirm this myself, but according to Nemesis the VDP has a basic prefetch mechanism for reads (which makes a lot of sense). Once you setup a read through the control port, the first unused external slot will fetch the requested word into an internal latch and mark a flag that the data is available. If you attempt to read and this flag is not set, the 68K will be forced to wait (via DTACK) until the data is available. AFAIK, you are correct in that FIFO writes take precedence over reads.

One consequence of the above, is that if you setup a write and then try to read the 68K will hang until the machine is reset.

mickagame
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Post by mickagame » Mon May 25, 2015 9:26 pm

Why thé 68k will hang? The read will be perform when write will be finish?

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Post by Mask of Destiny » Mon May 25, 2015 9:39 pm

I meant if you try to read from the data port after having setup a write via the control port. Since a read was not requested via the control port, the VDP will never actually read anything from VRAM and the 68K will be waiting for it to do so forever.

mickagame
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Post by mickagame » Tue May 26, 2015 7:51 pm

It make sens !!!

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