Megadrive: Custom-Cartridge including extra capabilities

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KanedaFr
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Post by KanedaFr » Thu Nov 27, 2014 4:46 pm

So if you write XXXX to A130YY, on the cart,
- TIME is low
- A0 to A7 is set according YY
- D0 to D15 is set according XXXX

you could add 16 additional IC on the cart, selectable with YY...
and all of this because of the DevRAM feature they left....
So great !

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Post by Chilly Willy » Thu Nov 27, 2014 6:45 pm

KanedaFr wrote:So if you write XXXX to A130YY, on the cart,
- TIME is low
- A0 to A7 is set according YY
- D0 to D15 is set according XXXX

you could add 16 additional IC on the cart, selectable with YY...
and all of this because of the DevRAM feature they left....
So great !

No longer ask why I like Genny : even 25 years later, I discover awesome features !
Slight corrections... it's A1 to A7 as there is no A0 (that's implied by the assertion of the byte lane strobes). And it's addressing 256 bytes of address space, which could be one IC, or could be 256 ICs, depending on how many address bytes they need.

Note - to be compatible with the 32X, any cart using /TIME must not respond to $A130EC. That's the 32X recognition register. The "standard" mapper also uses $A130F0 to $A130FF (the odd bytes of that range).

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Post by KanedaFr » Fri Nov 28, 2014 10:54 am

ah ah ! I totally messed up bytes and address ID !

And I thought we could use LWR to get from A0, no ?
Or we could only use odd address ?

So, to be safe, we have A13000 to A130ED

OK, so next problem : BUS CONTENTION

Does it mean a buffer is needed for each IC which could use the D0-D15 ?!

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Post by db-electronics » Fri Nov 28, 2014 1:13 pm

KanedaFr wrote:And I thought we could use LWR to get from A0, no ?
Or we could only use odd address ?
Due to big endianness, you get the odd addressed bytes when using only LWR
KanedaFr wrote: So, to be safe, we have A13000 to A130ED
As Chilly Willy mentioned, their is a 32X recognition register at $A130EC so you'd need to adjust your range slightly.
KanedaFr wrote: OK, so next problem : BUS CONTENTION

Does it mean a buffer is needed for each IC which could use the D0-D15 ?!
No, ICs which have a #CS line usually tri-state their outputs when not selected. All you'd really need is proper address decoding.

BUT, if you want to allow the Cart to address and use its own RAM at will then this RAM needs to exist within a memory space external to the 68k memory range. Therefore, there needs to be bus arbitration between the two when communication is required. It could be a mechanism similar to how the 68k can access the Z80 memory space, but only after a successful busreq.
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Post by KanedaFr » Fri Nov 28, 2014 3:14 pm

(sorry for the typo, of course I meant A130EB not A130ED )

my fear about bus contention is when using shared RAM to do some DMA for ex...

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Post by Chilly Willy » Sat Nov 29, 2014 6:58 pm

I figured you meant B instead of D. You should also respond to F0 to FF if the cart supports the mapper (and it really should). Basically, the cart should respond to everything EXCEPT EC to EF.

You can't use the lower byte strobe as an address line as the strobe provided on the cart slot is a WRITE strobe. Reads are always words with the data put onto the proper byte lane. Since we have both write strobes, writes can be bytes to either byte lane, or a word. If you aren't quite familiar with the 68000 bus, please consult the proper chapter of the 68000 hardware manual.

As to DMA contention, you have two choices: make the ram access fast enough that DMA isn't an issue, or make two sets of ram banks that run through the proper bus controller (more pins needed on the FPGA/CPLD, and more ram chips on the PCB). The former is how UMDK handles it, and the latter is how the SegaCD handles it. I don't think the SVP has been evaluated as to how the bus works, but I'd guess it halts during DMA.

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