How does the GDB link work?

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legacy
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How does the GDB link work?

Post by legacy » Wed Jan 28, 2015 12:11 am

hi
great project, i like it :D

i have not understood: do you have a gdb-stub running in the m68000 ?
if so, can i see the gdb stub for the m68k ?
it may be useful in my tiny 68k home-made board =)

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Post by prophet36 » Wed Jan 28, 2015 9:05 am

This is covered in some detail on the home-page. The implementation relies on some host-side proxy code and a tiny 68000 monitor which implements a request-response control interface, allowing the host to control the 68000 by writing commands and data to a region of the (dual-port) SDRAM, reading responses back from the same region, orchestrated by a single semaphore.

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Post by legacy » Wed Jan 28, 2015 11:29 am

understood, it's a different working scheme, in my case i will implement a common minimal-gdb-stub, i will have to use the uart to get commands, you are using a sort of message passing, the usb-link-hw writes directly in ram, then the 68000 reads commands from there, in my case i have no dual port ram, no usb-link-hw, so i will get commands from the uart (it's an old ACIA 6850 chip @ 9600bps, too slow, i guess)

your idea is simply wonderful, i think i will try to use a dual port ram chip in the future, with an hw semaphore an something like your fx2 usb-link.

68000 ---> dual port ram <------- fx2 usb-link

at the moment my board is a simple 68000 system composed by cpu with a few devices around (uart, pit, ram, rom), nothing special, 100% hobby activity :D

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Post by prophet36 » Wed Jan 28, 2015 12:20 pm

legacy wrote:i will have to use the uart to get commands
Right, in fact that was the setup that the designers of the GDB remote-serial-protocol envisioned. It was only later that they added the TCP/IP connectivity that my proxy uses.

The advantage of the UART implementation is simplicity (although you do have to write the GDB stub on the 68000 side which is doable but not exactly trivial) and flexibility.

The advantage of the dual-port SDRAM implementation (apart from speed, that you mentioned) is you can interrupt the CPU by writing a breakpoint into SDRAM whilst the CPU is running. But that kind of thing could equally well be done by your UART ISR.

Overall I don't think my approach is significantly better than yours. In fact in many ways your approach makes more sense.

Interestingly, the MegaDrive people who don't want to spend money on a UMDK cart could use your approach (and stub code) with the UART on the MD1 EXT port to get GDB debugging. I'd love to see someone get that working.

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Post by prophet36 » Wed Jan 28, 2015 12:51 pm

Incidentally...
legacy wrote:i will try to use a dual port ram chip in the future
it's not a dual-port RAM chip, it's just a regular $2 SDRAM. But I designed the memory-arbiter in the FPGA to have two request-response pipes, one connected to the 68000 and the other connected to the host via USB and FPGALink.

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Post by legacy » Wed Jan 28, 2015 2:24 pm

in my case i have seen a dual port chip, in DIP package, it's something like 8Kbyte with 2 posts, of {8bit data bus, address} each, with an without an hw semaphore.

(8 bit data, address, r/w) port1 -------ram -------- port2 (8 bit data, address, r/w)


it should be useful and easy, and relative cheap. It was a 7 euro chip.

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Post by legacy » Thu Jan 29, 2015 12:22 am

have you seen andy gdb-stub/m68k around ?
i have found something (to be fixed) for mips in the linux kernel
but i haven't found nothing for m68k

in case i will write it for scratches

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Post by Chilly Willy » Thu Jan 29, 2015 5:31 am

The Jaguar Skunkboard software, JServe, has a full m68k gdb stub. In fact, it works nearly identically how prophet36 described.

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Post by legacy » Thu Jan 29, 2015 2:36 pm

Jaguar Skunkboard ? never heard before, but it sounds good, does it have any repository of the gdb-stub/68k part ?

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Post by MintyTheCat » Thu Jan 29, 2015 7:11 pm

prophet36 wrote: Interestingly, the MegaDrive people who don't want to spend money on a UMDK cart could use your approach (and stub code) with the UART on the MD1 EXT port to get GDB debugging. I'd love to see someone get that working.
I intend to add this to AXLib.

Using one MD Port for debug is essentially how I did it before I used UMDK.

You do not even need a MD1 with the EXT Port as you can use any of the other two Ports if you do not need both ports for joypads that is.

Cheers,

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Post by Chilly Willy » Thu Jan 29, 2015 7:19 pm

http://www.harmlesslion.com/cgi-bin/sho ... skunkboard

Specifically, this arc: http://www.harmlesslion.com/zips/SkunkBoard.zip

Look in the GDB folder inside that arc (Skunkboard/Source/GDB).

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Post by legacy » Fri Jan 30, 2015 3:24 pm

a bit time ago i opened this topic describing a few debuggers, it was useful, and sometime i still read the thread because since then i have been designing my own one which i wanted to be called "swi_dbg"

it may be that thread is useful

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Post by legacy » Fri Feb 06, 2015 11:29 am

Image
SWI DBG debugger, ncurses interface (how my toy project looks)

i am still developing my own debugger interface for my SWI_DBG debugger (1)
it is still a not completed toy, but i is a very fun activity.
Its code is based on a text-editor i wrote a lot of time ago; i have arranged and improved it a bit
with the features of tracking the TAP machine

i have two TAP machines:
  • the client TAP, which has a the above text interface and it is able to send and receive uart packet to the target
  • the server TAP, which is very similar to the gdb-stub, but in my case it is a finite state machine pretty coded into the fpga, instead of a chunk of code running into the cpu, and "talks" through a protocol uart driven (ad 2Mbps)
the server TAP is able to stop the CPU, to trigger breakpoints, watchpoints, read/write memory mapped devices, read/write memory, do code-injection, read/write CPU's registers

it's very slow, the TAP protocol runs a 2Mbit per sec, which is ~ 200Kbyte of stream, but … the packet is not efficient about the payload, so … 10 bytes required to send uint32_t (4 byte, 32bit data size), which means … 20K packet per second, which means 80Kbyte of data per second: the payload is the 40% of the frame size

in other words, if you want to upload .text or .data (an application) the throughput is something like 80Kbyte per second, on a 2Mbips link: not so good!

it may be the next version of this protocol will improve the throughput, defining a shorter packet


(1) it is the debugger i want to implement for an fpga custom soft core, codename "Alise Core", it's handled as hobby research, it is implemented with a not pipelined multi cycle datapath, and its ISA (instruction set architecture) is something that looks like a mashup between MIPS R2K and motorola 88K, eight eight key, the first motorola RISC one.

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Post by MintyTheCat » Fri Feb 06, 2015 4:23 pm

Very nice indeed :)
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