SpritesMind.Net

Let me say this first: this is AWESOME.


Now that it's out of the way I have a few questions:

- Was a 4-layer board really necessary? doesn't seem the case to me, I've done heavier and denser stuff on 2 sided boards, even with BGA (50ball memory IC).

- Xilinx is expensive. I have the impression that Altera devices are cheaper.

- There's no way a small run could be costing $40/unit, just for the fact of this 4 layer board + spartan-6

- To simplify BOM you could possible merge resistors values together (I haven't checked the design, but the lower list of different values, the better)


.. I know I could just have browsed the source, but how much nanoseconds are there from the MD CE access pulse to databus valid (presented to the cart edge). I've done a dram cart a long time ago (my avatar) and VDP DMAs were a bit wrecked, as timing wasn't met. Otherwise the cart would run fine.

Jorge Nuno wrote:Let me say this first: this is AWESOME.

Thanks! Coming from you that means a lot to me!

Jorge Nuno wrote:Was a 4-layer board really necessary? doesn't seem the case to me, I've done heavier and denser stuff on 2 sided boards, even with BGA (50ball memory IC).

To simplify BOM you could possible merge resistors values together (I haven't checked the design, but the lower list of different values, the better)

I'm not great at board-level design and optimisation so it's very possible this is over-engineered. For my part this was really a learning project and it's pretty much "finished" as far as I'm concerned. Of course I will help others who want to reduce the footprint and/or switch to other components and develop it further, but I don't intend to do any more work on it.

Jorge Nuno wrote:Xilinx is expensive. I have the impression that Altera devices are cheaper.

Really? Cheaper than $7.40 per chip (for five)?

Jorge Nuno wrote:There's no way a small run could be costing $40/unit, just for the fact of this 4 layer board + spartan-6

Depends what you mean by "small". The $40 price is roughly what I paid for enough PCBs and components to make ten, mostly ordering from eBay and AliExpress, with PCBs from Hackvana.

Jorge Nuno wrote:I know I could just have browsed the source, but how much nanoseconds are there from the MD CE access pulse to databus valid (presented to the cart edge). I've done a dram cart a long time ago (my avatar) and VDP DMAs were a bit wrecked, as timing wasn't met. Otherwise the cart would run fine.

I don't use /CE at all, I do all my own address decoding, and just use /OE and /UDSW & /LDSW to trigger reads & writes. Writes can be pipelined so the timing is not critical, but for reads I long ago measured the worst-case assert time for /OE at 7 cycles @48MHz, and the worst-case deassert time also at 7 cycles @48MHz. The raw stats I gathered are here: http://www.swaton.ukfsn.org/temp/stats.txt. For example, the first line says I counted 264865 occurrences where /OE was asserted for 7 cycles @48MHz.

But that only gives the assert time; the real timing is tighter. The memory controller does one read in 4 cycles @48MHz, and there's another cycle used for synchronisation of the MD signals to the 48MHz clock. Then there's the traversal time through the level converters (in both directions) to take into account, and the setup time at the MD (I don't know what value this is, but it's certainly nonzero).

To achieve this latency I schedule all memory I/O on the MD strobes, so when the MD does a read or a write, it first services that, then it services any outstanding requests from the host (making the SDRAM essentially dual-port) and finally it does a refresh cycle. The result is I do far more refresh cycles than is necessary, but the upshot is I can actually meet the very tight latency requirements of the short DMA cycles.

Hope this helps!

prophet36 wrote:

Jorge Nuno wrote:Xilinx is expensive. I have the impression that Altera devices are cheaper.

Really? Cheaper than $7.40 per chip (for five)?

I'd say much cheaper. :3 Anyway, AWESOME project!

Not sure that's a great comparison. The Cyclone II is pretty old at this point whereas the Spartan 6 is Xilinx's newest low end series. Cyclone IV is Altera's competing device family.

Mask of Destiny wrote:Not sure that's a great comparison. The Cyclone II is pretty old at this point whereas the Spartan 6 is Xilinx's newest low end series. Cyclone IV is Altera's competing device family.

Delivered

Honestly I don't think there's much difference in price/capacity/performance between Xilinx and Altera. And the underlying FPGALink stuff works perfectly well on both, too. However, the vendor tools do make some difference - especially for small projects like this, the Altera tools are much faster.

Of course you're welcome to switch vendors, but IMHO your time would be better spent adding missing features like game-saves and some better analysis tools for the bus-cycle trace-log (currently pretty much grep & perl!).

Thanks for the answers. Another question:

Why is it a 2-board setup


And yes ISE sucks in comparison with Quartus.. it's just so bloated everywhere. Also notice that Xilinx CPLDs have stopped in time, even though they have limited usability.

On a DMA or z80 access, how do you check if a new access is made (since OE is held low) during a DMA burst (32 transfers AFAIK), do you compare the new address with a previous?

It's a two-board setup because the FPGA board is general-purpose; I designed it so it can be used in several other projects (I'm only tangentially interested in the MD).

I have not seen evidence of /OE held low for multiple addresses. If you give me some code that does it I'd be happy to run it and send you the trace-log. Needless to say, none of the commercial games that I've tried exhibit obvious problems.

Ahh ok, so it's an universal fpga devboard. Bonus points for circuit reutilization there.

Forget about the OE being low, it is CE that does that on a DMA, it's low for a burst while OE toggles. My bad here

Phew. You had me worried for a moment there.