Super Magic Drive research thread

Ask anything your want about Megadrive/Genesis programming.

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tcdev
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Post by tcdev » Tue Jan 25, 2011 11:59 pm

KanedaFr wrote:It would be cool to be able to dump Altera code, so anyone could burn a new one if damaged....
Unless it's possible to dump it, this part can't be fixed :(
AFAIK you can't buy them anymore anyway...

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Jorge Nuno
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Post by Jorge Nuno » Wed Jan 26, 2011 12:00 am

So the only solution is to figure out what it does exactly and get a new replacement part. Good luck

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Post by KanedaFr » Wed Jan 26, 2011 12:07 am

http://cgi.ebay.com/ALTERA-EP1810LC-EP1 ... 0696022923
http://cgi.befr.ebay.be/CMOS-EPROM-base ... 3a5fe935bc
:lol:
Internet is POWAAAAAAA!! ;)

I first thought it was "only" a multi AND/OR IC so that I "only" had to test every input (and see the output) :)

but the registers part is still not clear for me so I assume it's far to be so easy ;)
Last edited by KanedaFr on Wed Jan 26, 2011 12:09 am, edited 1 time in total.

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Post by tcdev » Wed Jan 26, 2011 12:09 am

Jorge Nuno wrote:So the only solution is to figure out what it does exactly and get a new replacement part. Good luck
I wouldn't be surprised if Charles could already tell you exactly what it does. AFAIK it's primarily address decoding, byte-lane steering, chip-select generation and DRAM refresh control.

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Post by Jorge Nuno » Wed Jan 26, 2011 2:02 am

Thats a rough description, but the accurate signal timings and relationship with inputs and the current state is what its needed.

Even if the chip was readable, what would we do with with the jedec file? Is the internal physical layout known? « for porting into a more recent IC

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Post by tcdev » Wed Jan 26, 2011 2:12 am

Jorge Nuno wrote:Thats a rough description, but the accurate signal timings and relationship with inputs and the current state is what its needed.
Obviously.
Jorge Nuno wrote:Even if the chip was readable, what would we do with with the jedec file? Is the internal physical layout known? « for porting into a more recent IC
I don't think there's any utility in trying to replace it, since you'd have rip out the socket and replace it with a daughterboard since you probably won't find a device with the same pinout.

The effort involved would be better spent designing a clone from scratch, using SRAM for example.

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Post by Charles MacDonald » Wed Jan 26, 2011 2:15 am

tcdev wrote:
Jorge Nuno wrote:So the only solution is to figure out what it does exactly and get a new replacement part. Good luck
I wouldn't be surprised if Charles could already tell you exactly what it does. AFAIK it's primarily address decoding, byte-lane steering, chip-select generation and DRAM refresh control.
I think we know what the EPLD does in a general sense, but don't really know the specifics. On the other hand maybe there isn't much of a need to know, unless there's some real demand for duplicating EPLDs. :)

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Post by KanedaFr » Wed Jan 26, 2011 8:22 am

In fact, I was so sad to find my SMD broken that I know want to be sure I'll be able to fix it if it ever broke again :lol:
From what I see, you can fix everything but this EPLD... (note I didn't investigate the DRAM board yet)

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Post by KanedaFr » Sun Jan 30, 2011 11:39 am

Ok...
so this morning, I checked everything which go to the DRAM connector.
2 notes I would like you to confirm

1/ from my test CRT.VD10 and CRT.VD11 are switched...
U4's B3 go to Connector's pin 7 and U4's B4 to pin 5

2/ CRT.VA20 is on pin 8 of the cart connector, not pin 7...(which seems right with cart connector pinout)

I double/triple check these so I think I didn't make a mistake....but I'm such a newb at this....;)


since the 40 pins are correctly working (it was a good(?) surprise when you look the state of the traces!), I looked to the dram board....
First, mine is different from you two's!
see http://gendev.spritesmind.net/img/smd/P1060030.JPG and http://gendev.spritesmind.net/img/smd/P1060031.JPG for HD pic
Second, there is ugly green and brown color everywhere so I suspect it needs some cleaning!

It still doesn't explain why it's unable to load a game from cart... I'll try to find more thanks to tcdev's disasm this week...

Man...I wonder if I'll be able to repair it ... :cry:

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Post by tcdev » Sun Jan 30, 2011 6:23 pm

KanedaFr wrote:see http://gendev.spritesmind.net/img/smd/P1060030.JPG and http://gendev.spritesmind.net/img/smd/P1060031.JPG for HD pic
Second, there is ugly green and brown color everywhere so I suspect it needs some cleaning!

It still doesn't explain why it's unable to load a game from cart... I'll try to find more thanks to tcdev's disasm this week...
It looks like you have quite a bit of corrosion on your connector. If you look into the DRAM board connector socket on the SMD main board, I suspect you will also see a lot corrosion. That was the problem with mine - I had to remove it and replace it.

Unfortunately battey damage is nasty and doesn't stop when you remove the battery. The corrosion in the traces continues and is only accelerated when you apply power. There are ways to try to minimise the effects.

Good luck and yes, you shouldn't need the DRAM board just to play carts!

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Post by KanedaFr » Sun Jan 30, 2011 10:40 pm

Next week end : vinegar & water ! :)

about, SRAM, I'm trying to understand CAS et RAS....
when !RAS, it means you're sending MSB of address (A5 to A9) and when !CAS you're sending LSB (A0 to A4) ?
it's strange so I assume I'm wrong....

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Post by tcdev » Sun Jan 30, 2011 11:35 pm

KanedaFr wrote:about, SRAM, I'm trying to understand CAS et RAS....
when !RAS, it means you're sending MSB of address (A5 to A9) and when !CAS you're sending LSB (A0 to A4) ?
I'm assuming you really meant DRAM... not SRAM...

CAS stands for Column Address Select and RAS stands for Row Address Select. I'm not familiar with the specific address lines in question (I don't have the data sheet here and I'm about 7,000 miles from home atm) but the principle is correct, yes. Asserting each of the RAS/CAS lines directs the memory to latch that part of the address. After it has latched the full address, the data can be read/written on the data pins.

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Post by Chilly Willy » Mon Jan 31, 2011 12:44 am

KanedaFr wrote:Next week end : vinegar & water ! :)

about, SRAM, I'm trying to understand CAS et RAS....
when !RAS, it means you're sending MSB of address (A5 to A9) and when !CAS you're sending LSB (A0 to A4) ?
it's strange so I assume I'm wrong....
As tcdev mentioned, RAS and CAS are used for DRAM, not SRAM. ALL the address lines are used. When /RAS is asserted low, A0-A9 holds the row inside the DRAM to be accessed, and when /CAS is asserted low, A0-A9 holds the column from the row to connect to the data bus.

If you are trying to run SRAM off a DRAM bus with RAS/CAS, you'll need to latch the address on the associated strobe. When RAS is asserted, you latch A0-A9 into A10 to A19 to the SRAM, and when CAS is asserted, latch A0-A9 into A0-A9 to the SRAM. You would also then assert the chip enable as you now have the full address.

DRAM used a multiplexed address scheme to save pins. It fit with the way DRAM worked... latching one axis enable, then the other as you cannot do both at once (the major difference between DRAM and SRAM).

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Post by KanedaFr » Mon Jan 31, 2011 8:24 am

thanks
yes of course, I talked about DRAM.
it makes sense = 2^10 * 2^10 = 1M....


Do you know if SMD use !UB_CAS and !LB_CAS at the 'same' time ? This way it would be possible to use a 1M*8 DRAM...
Else it would need a SRAM like you describe and latch part of the adress according !UB/LB_CAS & !UB/LB_RAS ...
I ask because I suspect I'll need to replace the board ... :(

On a side note, I "almost" understand the logic of each pin (thanks to Charles first schem & additional info from tcdev) but CRT.VA20.....
why the DRAM board is connected to pin 8 of cart connector ?!

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Post by Chilly Willy » Mon Jan 31, 2011 7:45 pm

KanedaFr wrote:thanks
yes of course, I talked about DRAM.
it makes sense = 2^10 * 2^10 = 1M....


Do you know if SMD use !UB_CAS and !LB_CAS at the 'same' time ? This way it would be possible to use a 1M*8 DRAM...
Else it would need a SRAM like you describe and latch part of the adress according !UB/LB_CAS & !UB/LB_RAS ...
I ask because I suspect I'll need to replace the board ... :(

On a side note, I "almost" understand the logic of each pin (thanks to Charles first schem & additional info from tcdev) but CRT.VA20.....
why the DRAM board is connected to pin 8 of cart connector ?!
/UB_CAS and /LB_CAS has to do with writing specific byte lanes, not the address. One is the upper byte (MSB of the word), and the other the lower byte (LSB of the word). When you don't assert CAS to DRAM, you wind up doing a RAS-only refresh cycle, so I suppose they found the easiest way to control writing was to OR the /CAS with the write strobe so that one byte gets the full address while the other does a refresh cycle.

As to why it needs A20... remember that the cart port is a WORD bus, and only A1 on up are available. So while the DRAM is getting a multiplexed address called A0 to A19, they come from the actual lines A1 to A20.

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