HBlank wrong hardware behaviour
Posted: Fri Jan 07, 2022 9:34 am
Hello guys, its been a while. I'm playing arround with hBlank and vblank trying to undestand how really works, so i made a simple test (code bellow):
Drawing background plane every odd line. I've tried the output on the emulator and works just as expected. But then i move to real hardware and some sync problem appears.
The next 3 screenshots are from, mame emulator, rom in a nomad using UMDK, and rom in a megadrive using everdrive.
Working correctly
Nomad, Note the aout of sync column. (Ignore UMDK mensage, also the banding, this console need a recap.)
Megadrive (megazord actually) on a tv, same problem.
Con someone give me some advice on what im doing wrong? This is the code, its very simple:
Drawing background plane every odd line. I've tried the output on the emulator and works just as expected. But then i move to real hardware and some sync problem appears.
The next 3 screenshots are from, mame emulator, rom in a nomad using UMDK, and rom in a megadrive using everdrive.
Working correctly
Nomad, Note the aout of sync column. (Ignore UMDK mensage, also the banding, this console need a recap.)
Megadrive (megazord actually) on a tv, same problem.
Con someone give me some advice on what im doing wrong? This is the code, its very simple:
Code: Select all
move.l #0xC0000003, VDP_CONTROLPORT ;write cram p0 c0
.loop
bsr .HblankStart
move.w #0x0000, VDP_DATAPORT ;push color black to p0 c0
bsr .HblankEnd
bsr .HblankStart
move.w #0x000E, VDP_DATAPORT ;push color red to p0 c0
bsr .HblankEnd
bra .loop
.HblankStart:
move.l VDP_CONTROLPORT, d1 ; Vdp statatus register to d0
btst #VDP_STATUS_HBLANK_BIT, d1 ; test Hblank bit
bne .HBlankStart ; Wait loop on condition
rts
.HblankEnd:
move.l VDP_CONTROLPORT, d1 ; Vdp statatus register to d0
btst #VDP_STATUS_HBLANK_BIT, d1 ; test Hblank bit
beq .HBlankEnd ; Wait loop on condition
rts