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Re: M68K Bus Control and Vdp
Posted: Wed Dec 11, 2019 4:20 pm
by Miquel
No word access: Z80 memory space can only be accessed by the 68k in byte address mode, and that has to mean something.
Re: M68K Bus Control and Vdp
Posted: Wed Dec 11, 2019 5:27 pm
by mickagame
Miquel wrote: ↑Wed Dec 11, 2019 4:20 pm
No word access: Z80 memory space can only be accessed by the 68k in byte address mode, and that has to mean something.
Does that mean that accessing Z80 space in word mode (UDS and LDS selected) does not have any effects?
![Question :?:](./images/smilies/icon_question.gif)
Re: M68K Bus Control and Vdp
Posted: Wed Dec 11, 2019 10:54 pm
by Miquel
I don’t know, my GUESS is: z80 bus is 8bit so you can't connect a word, it can’t be a buffer since there is no independent device working, therefor only d0-d7 are connected. The other option is d8-d15 are connected but that will be an unnecessary misconduct.
move.b d0, 0xA00000 -> works for sure
And following that guess:
move.w d0, 0xA00000 -> only transfers low byte
move.l d0, 0xA00000 -> transfers two bytes, the lower ones on the 2 words
The problem is when you are transferring something to the z80 memory, you do a loop, like:
move.l #0xA00000, a1
Loop:
move.b (a2)+, (a1)+
dbra.w d0, Loop
But instead if you use word or long access, information is lost, so makes no sense to use them.
Re: M68K Bus Control and Vdp
Posted: Wed Dec 18, 2019 12:37 pm
by HardWareMan
IC5 315-5309 is used to unite the M68K and Z80 buses. It used
ZA[7:0] and ZD[7:0] from
Z80 side and
VA[7:1] and VD[15:0] from
M68K side. For setting mode for access through it used this set of control signals:
nCAS0,
nLWR,
nHL from M68K side and
nZTOV,
nVTOZ form bus arbiter
IC4 315-5364. So, using only
nLWR it definitly can't do
VD[15:8] or "High byte" write to the
Z80 domain.
![Image](https://i.imgur.com/h5FtHSm.png)
Re: M68K Bus Control and Vdp
Posted: Thu Dec 19, 2019 7:26 pm
by Eke
From gen-hw.txt
Word-wide writes
When doing word-wide writes to Z80 RAM, only the MSB is written, and
the LSB is ignored:
0000: AA BB CC DD ; Z80 memory
move.w #$1234, $A00000 ; do a word-wide write
0000: 12 BB CC DD ; result
Word-wide reads
A word-wide read from Z80 RAM has the LSB of the data duplicated in the MSB.
0000: AA BB CC DD ; Z80 memory
move.w $A00000, d0 ; do a word-wide read
d0 = $AAAA ; result
It can be confirmed by a quick test but above notes suggest that when /ZTOV is asserted, IC5 simply copies VD15-VD8 to ZD0-ZD7 (and when /ZTOV is asserted, it copies ZD0-ZD7 to VD15-VD8 and VD7-VD0). It makes no difference on byte write since 68k duplicates VD7-VD0 on VD15-VD8 and on word writes, it explains why MSB is written to Z80 area.
Also, doing a byte write to an even address in Z80 area from 68k (so with only /UWR asserted) is working fine, which suggests that /LWR is not even used when IC9 transfers data between Z80 and 68k buses, only /ZTOV and /VTOZ
/LWR is likely only used for writes to I/O registers (which are indeed accessible at odd adresses only).
Re: M68K Bus Control and Vdp
Posted: Fri Dec 20, 2019 8:53 pm
by Miquel
Program tested:
Code: Select all
0: move.w #0x00FF, 0xA00000
move.b 0xA00000, d0
jeq 0b
Tested on (I could be using somewhat old versions of emulators):
Gens KMOD: copies low byte
Fusion: copies high byte
Regen: copies low byte
Real hardware TMS Asian: copies low byte
Conclusion: it doesn’t matter since all those emulator have a HUGE range of compatibility, but it copies low byte (unless it changes depending on hardware revision…).
Re: M68K Bus Control and Vdp
Posted: Sat Dec 21, 2019 4:42 pm
by Eke
That's weird because I found a test ROM made by Mask of Destiny (see
this post ) which actually tests word writes from 68k to Z80 RAM and it actually verifies the opposite (it writes $BEEF to $A00002 then expect $BE to be read from $A00002 as byte, while $A00003 retains previous value).
You could think that the behavior differs on your hardware revision (not sure which model a TMS Asian is though) as you suggest but the thing is, Regen passes the above test ROM (which means it actually copies upper byte), which does not match with you observed results.
Maybe you could post your own test ROM so it can be checked but I suspect you forgot to request Z80 bus before accessing it, which would actually return open bus (next instruction usually) on Z80 RAM read, and therefore gives misinterpreted results.
Re: M68K Bus Control and Vdp
Posted: Sun Dec 22, 2019 1:38 am
by Miquel
I believe I do it with the Z80 stopped, but you could be right, let me check it again in a day or so.
Re: M68K Bus Control and Vdp
Posted: Sun Dec 22, 2019 4:41 am
by Miquel
You are right Eke, I thought that on cold start both z80 was stopped and without bus, so a fast position to check it, but it’s only stopped/reset.
Just redid the experiment making sure the bus was acquired by the 68K and:
Fusion: high byte
Regen: high byte
Gens KMOD: low byte
MD1 Asian TMS: high byte
Down is the test rom, grey: high byte, brown: low byte, white: anything else
Re: M68K Bus Control and Vdp
Posted: Sun Dec 29, 2019 5:24 pm
by HardWareMan
Eke wrote: ↑Thu Dec 19, 2019 7:26 pm
It can be confirmed by a quick test but above notes suggest that when /ZTOV is asserted, IC5 simply copies VD15-VD8 to ZD0-ZD7 (and when /ZTOV is asserted, it copies ZD0-ZD7 to VD15-VD8 and VD7-VD0). It makes no difference on byte write since 68k duplicates VD7-VD0 on VD15-VD8 and on word writes, it explains why MSB is written to Z80 area.
Also, doing a byte write to an even address in Z80 area from 68k (so with only /UWR asserted) is working fine, which suggests that /LWR is not even used when IC9 transfers data between Z80 and 68k buses, only /ZTOV and /VTOZ
/LWR is likely only used for writes to I/O registers (which are indeed accessible at odd adresses only).
I think you are wrong. Look at pic above.
Z80 uses
ZA[7:0] and
ZD[7:0] and that give us 256 bytes.
M68K uses
VA[7:1] and
VD[15:0] and that give as 127 words or still 256 bytes. But.
When
Z80 reading and take
M68K bus it indeed do 16 bit access.
ZA[7:1] goes to
VA[7:1], and
ZA[0] use to choose which byte need to be read:
ZD[7:0] = (ZA[0]) ? VD[7:0] : VD[15:8]. When
Z80 write,
ZA[7:1] goes to
VA[7:1] and
ZD[7:0] goes to
VD[15:8] or
VD[7:0] according to
ZA[0] and
UWR or
LWR will asserted.
Now, when
M68K request
Z80 bus, same process will be happen, except one thing.
M68K hasn't
VA[0], but it have two data strobe:
UDS and
LDS. So, when
M68K whant to access to the
Z80 bus,
VA[7:1] goes to
ZA[7:1],
VD[15:8] or
VD[7:0] goes to/from
ZD[7:0] according to
ZA[0]. And
ZA[0] uses recovered
VA[0] from
LDS/
UDS.
My suggestion is that
IC4, the bus arbiter, do all that
VA[0] recovering magic: it have access to
UDS,
LDS and
ZA[0]. And it uses only
UDS: it can be directly routed to the
ZA[0]. So it explain what happens when you do byte or word write:
1.
UDS=0 and
LDS=1 ->
ZA[0]=0, upper byte
VD[15:8] goes to/from
ZD[7:0]
2.
UDS=1 and
LDS=0 ->
ZA[0]=1, lower byte
VD[7:0] goes to/from
ZD[7:0]
3.
UDS=0 and
LDS=0 ->
ZA[0]=0, upper byte
VD[15:8] goes to/from
ZD[7:0] and lower byte
VD[7:0] is ignored
And as
M68K with word write increases address by 2, only upper bytes gets to even addresses
Z80.
I've been always wonder, why arbiter uses
ZA[0], now I know why.
Re: M68K Bus Control and Vdp
Posted: Mon Dec 30, 2019 8:38 am
by Eke
I've been always wonder, why arbiter uses ZA[0], now I know why.
Yes, it also seemed the most logical to me that ZA0 is connected to /UDS by the bus arbiter on 68k access to Z80 bus, my theory did not contradict that. The question was more to know if the I/O chip uses ZA0 to know which byte (VD15-VD8 or VD7-VD0) to copy to ZA0-ZA7 or if it copies VD15-VD8 by default.
The latter case seemed more simple as hardware design to me initially as it makes no difference on byte writes (since both upper and lower bytes are identical on 68k output), however, now that I think a bit more about it, when Z80 reads from 68k bus, it needs to get either upper or lower byte from VD15-VD0 depending on ZA0 so you are right, it indeed makes more sense that the I/O chip looks at ZA0 in any cases (since it can not distinguish between 68k writes to Z80 bus and Z80 reads from 68k bus, it's still the same /VTOZ signal asserted in both cases).
3. UDS=0 and LDS=0 -> ZA[0]=0, upper byte VD[15:8] goes to/from ZD[7:0] and lower byte VD[7:0] is ignored
It is ignored when transfering from 68k to z80 bus but on 68k word reads, test ROM showed that ZD7-ZD0 is also copied to VD7-VD0. It is likely also the case when Z80 writes to 68k bus (/ZTOV asserted in both cases).
Re: M68K Bus Control and Vdp
Posted: Fri Apr 28, 2023 9:35 am
by HardWareMan
Okay. The decapping really confirmed the fact that the ZA[0] pin of arbiter 315-5364 is indeed a /UDS signal synchronized with the VCLK signal.