Here is the full list of 68k patents I found, with links.
- US4296469: Execution unit for data processor using segmented bus structure. Everyone already knows about this one.
- EP0011374B1: Execution unit for data processor using segmented bus structure. The European version is newer, but does not seem to add any new information. I haven't compared in detail, though.
- US4325121: Two-level control store for microprogrammed data processor. Last one everyone knows about; this is the source of microcode everyone looks for. Page 164 has cut microcode boxes.
- EP0011412B1: Bipartite control store for microprogrammed data processor. The European version. The microcode listing has a full version of page 164 of US patent. Some pages are more legible, others less. The microcode is subtly different: some are layout differences, but divu/divs microcode is subtly different. There may be more differences; but it still has dcnt, and trap microcode is different from Galibert's microcode dump.
- US4307445: Microprogrammed control apparatus having a two-level control store for data processor. Everyone knows about this one too. I could find no European version.
- JP6236256B2, the Japanese version is interesting: it is classified as a version of US4307445, but it is much closer to US4325121, and has a full microcode listing! In here, we can see that the microcode is subtly different: some are layout differences, but the divu/divs microcode is subtly different. There may be more differences; but it still has dcnt, and trap microcode is different from Galibert's microcode dump. I downloaded every page from the JPO and compiled a PDF of it.
- US4312034: ALU and condition code control unit for data processor.
- US4338661: Conditional branch unit for microprogrammed data processor.
- US4342078: Instruction sequence decoder for microprogrammed data processor and method.
- US4348722: Bus error recognition for microprogrammed data processor. This one has a very interesting tidbit on exception processing for address error:
"An address error terminates the cycle somewhat differently as a result of the way the address error signal is generated. A DBYTE latch is used in conjunction with the AOBLO signal to generate an address error. The address error signal is active from the first T1 of the error cycle to the first T1 of the next memory reference cycle. An address error does not reset the bus control logic; instead, it leads it to believe that both a data transfer is complete (i.e., DTACK) and a permission to stop has been received from the control unit" (emphasis added)
Meaning that the bus cycle finishes before the address error triggers. Searching a bit, this has been observed in Atari STE in the Atari forums (see here). Note that the cycle counts given prove the information of the patent, but they are not truly representative of the 68k; the Atari STE only allows the 68k to access the bus on the last two microcycles of every group of 4, meaning instructions generally are rounded up to multiples of 4 microcycles.
- US4349873: Microprocessor interrupt processing.
- EP0011375A1: Multi-port RAM data structure for data processor registers. Referenced in some of the US patents, I only found the European version.