Genesis / Megadrive Maximum Memory Map

[Mask of Destiny]

Did I ask help with building logic?
I just don't know any info about how Write Access is done. May be there is different timing? May be something else? May be you can't write words: bytes only. May be you can't write bytes: words only.

!UDSW indicates a write to the upper byte of a word, !LDSW indicates a write to the lower byte of a word. For a word-wide write both will be driven low. You can support both byte and word writes with these signals. If you're using 2 8-bit wide RAM chips you would tie the appropriate write strobe to the !WE pin of the respective RAM chip. For a 16-bit RAM you may need to OR the two together to generate a word-write signal.

Many of EEPROM-s needs to initialize programmable mode. Is they supported? And a lot more questions.

They're supported in the sense that it's possible to write one wired up to a Genesis cartridge. You can't treat it like RAM though. Programming is a somewhat involved operation.

But what about RAM (without S): it's known that RAM in common sense needs to be rewrited frequently to restore data, otherwhise data would be lost. Is it needed for MD? Do I need to add some microcontroller which would update RAM to save data?

DRAM generally adds 2 complications. One is refresh (which you mentioned) and the other is that the address lines are typically multiplexed. So there's a row address strobe and a column address strobe. Typically you'll have some kind of memory controller between the CPU and the DRAM that deals with both problems. The Megadrive does have some limited support logic that makes interfacing DRAM a little easier, but I don't know much about it. SRAM is cheap enough these days that I'm not sure it's worth the trouble unless you're making a lot of carts with a rather high memory capacity (like say the Mega Everdrive). I can get an 8Mbit 5V SRAM in a TSOP package for less than $6 at Digikey.

If you want to add SRAM, I can tell you, if you sure that /WR is triggered on whole M68k range (it can be tested), then you can make whole 4MB SRAM and with 4MB ROM too (within same addresses).

!UDSW and !LDSW are generated by the 68K directly so they should be present for the entire 16MB address range.

[Jorge Nuno]

No, the 68k has byte RW strobes, not just writes: UDS and LDS.
The cart slot is given 2 write strobes (LWR and UWR) and they come from the VDP. They are asserted both from 68k writes and z80 writes.

Using time to mask all rom in place for a 4MB ram will give you a big problem: suddenly the 68k loses it's code source.

[r57shell]

But you can always run code from RAM .

[Chilly Willy]

But you can always run code from RAM .

Well, you have to be careful of things like interrupts as well. You need to: a - make sure interrupt handlers are not in the rom area and don't use the rom area, b - turn off ints while ram is switched, or c - put the interrupt handlers in the ram as well.

It's the same issue as save ram has in carts that are bigger than 2MB. Since the rom overlaps the save ram area, you have to worry about interrupts and their handlers winding up in the overlap. If you make ALL the rom area switch to ram, it's all overlapping, and you have to worry all the more.