Quick question

walker7 · Post by **walker7** » Sun Aug 11, 2013 9:34 pm

How many 68000 CPU processor cycles occur in one frame (that is, between one VBlank and the next VBlank)?

TmEE co.(TM) · Post by **TmEE co.(TM)** » Sun Aug 11, 2013 9:39 pm

488 * 313 for 50Hz and 488 * 262 for 60Hz

doragasu · Post by **doragasu** » Mon Aug 12, 2013 4:09 pm

Interesting data. I'll use this thread to ask a related question:

How many 68000 cycles occur in the HBLANK interval (From when the HBLANK interrupt occurs to the beginning of the next line drawing). I think I read somewhere that there are only 36 cycles (leaving room only for a few asm instructions), but I'm not sure.

TmEE co.(TM) · Post by **TmEE co.(TM)** » Mon Aug 12, 2013 4:13 pm

By definition one line is 64µs which of 52µs are visible in PAL. 488 / 64 = 7.625
7.625 * 52 = 396.5
488 - 396.5 = 91.5

So you have roughly 91 cycles that won't be seen. However there's only 2 or 3 access slots in the HBL area so there's not a whole lot you can do. You can disable rendering and lose some/most/all sprites for that line in exchange of free time to do unrestricted DMA.

doragasu · Post by **doragasu** » Mon Aug 12, 2013 4:52 pm

Thanks a lot. You are a living MD encyclopedia

Do you have the numbers for NTSC?

Also why do you say you lose sprites for that line? Are you telling that if I disable rendering during HBLANK, do DMA and re-enable it before the end of HBLANK, sprites will not be properly drawn for the next line?

And a final question: if data is already inside VRAM, can I DMA it from VRAM to VRAM without restrictions during HBLANK, or is VRAM to VRAM DMA also restricted during HBLANK?

TmEE co.(TM) · Post by **TmEE co.(TM)** » Mon Aug 12, 2013 5:12 pm

NTSC should be basically same, both have same amount of cycles pre line and lines are basically same length in real life with minor difference.

Sprites are prepared during HBL which is why there's so few access slots. When you disable rendering you also disable sprite processing. So if you enter HBL, disable rendering and enable it again you have disrupted the sprite preparation process and when line actually starts there will be missing sprites.

VRAM to VRAM DMA has same restrictions as normal DMA but it is half as fast because it has to read a byte, then place a byte.
When the VDP shows image the VRAM is basically off limits, with onlf 18 access slots during an active line. There's 198 access slots in border and VBL lines because VDP is not doing anything then.

doragasu · Post by **doragasu** » Tue Aug 13, 2013 6:21 pm

Thanks a whole lot. I find this info really interesting!

I didn't know sprites are prepared during HBL, I thought VDP was idle during that time, but it makes sense it starts sprites preparation.

The fact than only 2 or 3 accesses to VRAM can happen during HBL makes me wonder... how can games accomplish effects like palette changes during HBL? E.g. water levels in Sonic games change more than 3 colours when crossing the water line, do they?

TmEE co.(TM) · Post by **TmEE co.(TM)** » Tue Aug 13, 2013 8:48 pm

Palette changes in those games continue to active line. You can see wrong colored pixels on real hardware in fixed locations on the water line. Those pixels show the currently being written color, and also show where the access slot is on the line.

mickagame · Post by **mickagame** » Wed Aug 14, 2013 6:45 pm

Read Nemesis Post Here :

viewtopic.php?t=1291&postdays=0&postorder=asc&start=15

doragasu · Post by **doragasu** » Thu Aug 15, 2013 3:06 pm

Wow, I never noticed the wrong pixels while playing Sonic games on my real Megadrive. I'll have to look closer.

Again thanks for the info. I think I have no more questions about timing right now

BTW, that Nemesis post is epic!