Question on Golden Axe II

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Near
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Question on Golden Axe II

Post by Near » Fri Apr 02, 2021 8:04 pm

I notice my emulator is getting a garbled "Sega" logo screen, and partially garbled intro screen immediately after it.

Looking at the trace, it loads d0 with #$ffffffe3, and then shortly after just starts spamming loop: move.l (a0)+,($c00000); dbf loop; instructions for big ~64K loops from ROM to VRAM, filling it with pure junk basically.

Image

I confirmed via Mednafen that it really does do this. Source+target address is correct, it really does spam hundreds of thousands of writes to the data port to send to VRAM. The VRAM address it's writing to loops around back to the beginning a few times even, so it's clearly nonsensical. I thought at first it'd be VDP FIFO limiting how much data it could get across, but Mednafen doesn't seem to emulate the FIFO. If I try to simulate 16-18 transfers per active display line, 85-105 transfers per blanking line, it just slows down how long before the garbled "Sega" screen appears, and doesn't really affect the result much.

I must be missing something here. Anyone here wrestle with this game before by chance? ^-^;

Eke
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Re: Question on Golden Axe II

Post by Eke » Sat Apr 03, 2021 7:37 am

From memory, this game attempts to write to VRAM after setting the CTRL port for a register write, without setting the address and control registers in between. The solution is to still update the address (lower 14 bits) and code (lower 2 bits) registers when a VDP register write occurs, and ignore data port writes when the code register value is not a valid write command value (0x1, 0x3 or 0x5).

Near
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Re: Question on Golden Axe II

Post by Near » Sat Apr 03, 2021 11:00 am

Shoot, I do that too.

Code: Select all

auto VDP::writeDataPort(n16 data) -> void {
  io.commandPending = false;

  //DMA VRAM fill
  if(dma.io.wait) {
    dma.io.wait = false;
    dma.io.fill = data >> 8;
    //falls through to memory write
    //causes extra transfer to occur on VRAM fill operations
  }

  //VRAM write
  if(io.command.bit(0,3) == 1) {
    auto address = io.address.bit(1,16);
    if(io.address.bit(0)) data = data >> 8 | data << 8;
    vram.write(address, data);
    io.address += io.dataIncrement;
    return;
  }
  
  ... //same thing for VSRAM and CRAM
}
Well, this puts me on the right path to where the problem is. Thank you very much for the insight! I'll keep giving it a go.

Eke
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Re: Question on Golden Axe II

Post by Eke » Sat Apr 03, 2021 11:46 am

That's only the 2nd part (ignoring invalid command values on data port writes).

Looking at Higan sourcecode, the error is here:
https://github.com/higan-emu/higan/blob ... o.cpp#L154

io.command[1:0] and io.address[13:0] should also be updated in case of register write

Near
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Re: Question on Golden Axe II

Post by Near » Sun Apr 04, 2021 8:57 am

That was exactly it, thank you so very much!

This hardware is really giving me a lot of trouble it seems ^-^;

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