Megadrive1 overclocking using EDClk
Posted: Sat Jan 10, 2009 12:35 am
A little detail about the EDClk:
It's not a pure clock signal - during horizontal synchronization it's frequency is MasterClk/5 (~10.6MHz), but in active-video it's MasterClk/4 (~13.3MHz), I think it's an input to the VDP, after coming from a low-passfilter, which means that during active-video the clock amplitude is smaller. Before the filter the signal is good (constant amplitude), and that includes the B15 pin from the cartslot.
Now some info about the DTAck signal; probably most of the megadrive hardware lovers know this:
Each active device "responding" to the CPU drives the signal low (VDP/BUScontroller/Extra hardware at the cartridge port) but it's never driven high, (to avoid short-circuit) so a pull-up resistor is required (and there is one of 2.2k).
The problem: This signal has a huge capacitance, so DTAck will quickly go low, but the rise is slooowwww... (sometimes it doesn't reach Vcc/2 using EDClk as a CPU clk and sinks again )
This means that:
CPU accesses ROM -> DTAck activated (low);
CPU accesses IO, DTAck is still low (or below trigger level);
CPU continues to run, but the R/W probably missed!
Solution: make DTAck rising edge faster... How? Replacing 2.2K with a 910Ohm resistor or leave the 2.2K resistor and connect one in parallel with 1.8K. (Average current flow when DTAck is forced-low is 5.5mA).
In normal occasions DTAck is activated one cycle (~130nanoseconds) after AS, never less so don't worry about using slow-motion-memories as long as they are faster than that, it's safe. (actually the address is already set-up before AS, so maybe 150ns are accepted).
MD1 CPU sucessfully overclocked to... errr.. EDClk MHz, fully stable and with sound of course. No shitty halt switches, just hardwire the CPU with EDClk before the filter, and it's fine.
Remember that the memory accesses aren't affected with the overclock, unless you snap in some modern/faster memories and sink DTAck before 130ns yourself.
Coming in near future is a picture of new/old DTAck waveform.
[speculation]
Also I beleive that EDClk is always MasterClk/5 in 256 pixel mode...
[/speculation]
It's not a pure clock signal - during horizontal synchronization it's frequency is MasterClk/5 (~10.6MHz), but in active-video it's MasterClk/4 (~13.3MHz), I think it's an input to the VDP, after coming from a low-passfilter, which means that during active-video the clock amplitude is smaller. Before the filter the signal is good (constant amplitude), and that includes the B15 pin from the cartslot.
Now some info about the DTAck signal; probably most of the megadrive hardware lovers know this:
Each active device "responding" to the CPU drives the signal low (VDP/BUScontroller/Extra hardware at the cartridge port) but it's never driven high, (to avoid short-circuit) so a pull-up resistor is required (and there is one of 2.2k).
The problem: This signal has a huge capacitance, so DTAck will quickly go low, but the rise is slooowwww... (sometimes it doesn't reach Vcc/2 using EDClk as a CPU clk and sinks again )
This means that:
CPU accesses ROM -> DTAck activated (low);
CPU accesses IO, DTAck is still low (or below trigger level);
CPU continues to run, but the R/W probably missed!
Solution: make DTAck rising edge faster... How? Replacing 2.2K with a 910Ohm resistor or leave the 2.2K resistor and connect one in parallel with 1.8K. (Average current flow when DTAck is forced-low is 5.5mA).
In normal occasions DTAck is activated one cycle (~130nanoseconds) after AS, never less so don't worry about using slow-motion-memories as long as they are faster than that, it's safe. (actually the address is already set-up before AS, so maybe 150ns are accepted).
MD1 CPU sucessfully overclocked to... errr.. EDClk MHz, fully stable and with sound of course. No shitty halt switches, just hardwire the CPU with EDClk before the filter, and it's fine.
Remember that the memory accesses aren't affected with the overclock, unless you snap in some modern/faster memories and sink DTAck before 130ns yourself.
Coming in near future is a picture of new/old DTAck waveform.
[speculation]
Also I beleive that EDClk is always MasterClk/5 in 256 pixel mode...
[/speculation]