More 315-5313 unknown stuff (speculation)
Moderator: BigEvilCorporation
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And on pins 124-127, does the presence/absence of the sun changes anything?
Me too but that's almost impossible to find, but they must be connected to the address bus of an external CRAM and the CRAM data bus to the triple video DAC, the 315-5242, I'm sure of it...HardWareMan wrote: I want shematic diagram connections this pins on C2 machine....
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I will explain... If I don't enable the VDP bit, what do you get on these pins? Nothing more than garbage... that is because the VDP probably tri-state that "color bus" (It seems...) then the 68000 takes control of it and writes what it wants to CRAM (in the invisible protion of the screen, or else it would show color garbage)HardWareMan wrote:Cant see connection. If it external CRAM, then must be method to do write an palette in it. How? I want that damn shematic diagram...
PS So, how use it in Sega MD games? They dont use this bits, right?
How to enable them in Original MD games? I have bought FPGA that, among other things will spy the address $C00000 waiting for a 8BXXh on the data bus, but instead of let it go, it will set the relevant bit to enable that digital output..., I'm just waiting for the holiday to make it reality...
Of course I will have to spy CRAM DMAs to write them too in my external CRAM, I've already said something like this on the 1st post... but it was all speculating, now it seems to be more real...
BTW there is no schematic but there is this:
http://cgfm2.emuviews.com/txt/c2tech.txt
Also: the Color DAC, that 315-5242 schem in system 24:
http://www.geocities.com/vjkemp/sega/hrs.png
Could you post some pics/movie of the TV with those signals?
Thanks
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Bump2:
My implementation of the color part of the VDP
Main schematic:
http://trapalhadas.no.sapo.pt/VDPpalette.PNG
Address increment system:
http://trapalhadas.no.sapo.pt/Increment.PNG
Internal color ram:
http://trapalhadas.no.sapo.pt/Cram.PNG
LineDoublerBuffer is a FIFO memory, to replicate lines, for 480p output.
LAT8s are 8-bit latches.
It's still incomplete, but I will update the pictures along with the development of the schematics...
Any suggestions for completion/bug fixing will be accepted
My implementation of the color part of the VDP
Main schematic:
http://trapalhadas.no.sapo.pt/VDPpalette.PNG
Address increment system:
http://trapalhadas.no.sapo.pt/Increment.PNG
Internal color ram:
http://trapalhadas.no.sapo.pt/Cram.PNG
LineDoublerBuffer is a FIFO memory, to replicate lines, for 480p output.
LAT8s are 8-bit latches.
It's still incomplete, but I will update the pictures along with the development of the schematics...
Any suggestions for completion/bug fixing will be accepted