Page 2 of 2

Posted: Sun May 22, 2011 5:17 am
by HardWareMan
eteream wrote:You are right about PC inc. BUT your forget one thing, when you are calculating the EA you are not executing anything!
Where I'm talking about EA? I'm talking about PC, answering only to your words:
eteream wrote:There are some things uncovered in the 4,325,121 for example the damn PC:=PC+1, I really don't know how to fit it in this design without adding and extra adder.
When PC incrementation used? Yes, while opcode fetching wich contains more than one word.
Actually, it may not be PC only. This property can be provided to an output address latch register, the source of address bus. Then, using once calculated EA, we can do sequential access, without additional calculations of EA (eg, DWORD @EA is the WORD @EA and the Word @EA+1, right?).
Talking about number of cycles of opcode (wich described in M68KUM as N(R/W)) youre right.

Posted: Mon May 23, 2011 5:56 pm
by eteream
In case there is a collision:


As much as I can tell only shifts can overlap with fetch, but the fact is they wait 6 or 8 cycles to begin working.
Now i'm facing Z80 design, so 68k will be stopped for a while.

Now what I realize is CPUs are a lot simpler that many think. May be bucks make the difference.