HDD (or flash) instead of a CD, questions...

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KanedaFr
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Re: HDD (or flash) instead of a CD, questions...

Post by KanedaFr » Wed Jun 21, 2017 2:45 pm

yes, it's why this one was a problem for me... I didn't see the link between WFCK / LRCK /... and this one

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Re: HDD (or flash) instead of a CD, questions...

Post by KanedaFr » Wed Jun 21, 2017 9:11 pm

It's time for the CXD2500 to give me some headaches !

So, when the DSP finish to write the frame on buffer
- WFCK is put to low
- first bit of frame subchannel set on SBSO
- if it's the first frame of sector, SCOR is put to HIGH and subcode is first byte of the sync word : S0 ..and not P-W
- host starts so to read the subcode serialized (bit per bit) activating EXCK
- every time EXCK is raised to HIGH, the DSP shift the next bit (with a small <400ns window)

It's what I understand from the first timing chart avaible on CXD2500 (and some others reading). (see below)

Then, I reached the second timing chart....and I lost my mind ;)

Image

1/ the first bit is again pushed as a last bit....why ?!

2/ it seems the DSP only handle one of the 2 first frame (with S0 and S1)
Even more troublesome, this other time chart seems to tell the first frame is pushed at the end of previous sector
Image

3/ on the chart, it seems first sucode pushed is S0-S1,QRSTUVW
what does it means ?! it should be the 8 bits of S0 (or S1 if it's the second frame in fact, see 2/)

4/ side question, about WFCK. Does it means when LOW, frame is on buffer and when HIGH, frame is written to buffer ?
in this case, what is pushing SCOR when WFCK is high ? subcode of frame available on buffer BEFORE buffer was overwritted on WFCK on HIGH or just written frame?
Or buffer is able to write +/- 28 frames so no problem ? ;)

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Re: HDD (or flash) instead of a CD, questions...

Post by KanedaFr » Thu Jun 22, 2017 8:22 pm

i found this other Sony EFM Demodulator / subcode decoder (CX7933) diagram.

Image

It's clearly explain
1/ => shift register (loop)
4/ => the data to be serialized are on the shift register buffer

but it still doesn't explain 2/
SCOR = S0 | S1...so SCOR should be active on first AND second frame
perhaps the answer is on the S0 & S1 logic to first shift register...I don't uderstand what it's goal...

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Re: HDD (or flash) instead of a CD, questions...

Post by KanedaFr » Thu Jun 22, 2017 9:37 pm

OOOOOK
Another DSP datasheet seems to give me more details
Image
Image
It's not exactly the same (it push Q first, not P) but i think I got it know, based on previous post
When S0 is detected, SCOR is ready to be raised, which occurs as soon as S1 is detected (S0&S1)

So,...does the CXD2500 behave the same way ?
or dos i just need to raise SCOR on first (S0) and second frame (S1)....?
without better analysis, it would be hard to define the real mode :(
i'll while playing ;)

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Re: HDD (or flash) instead of a CD, questions...

Post by Eke » Fri Jun 23, 2017 1:10 pm

It's not exactly the same (it push Q first, not P) but i think I got it know, based on previous post
Beware that this last diagram is about different signals (SQCK/SQDT)- also present on CXD2500 chip (the latter is just named SQSO) - which are dedicated to Q-channel (with CRC verification): that was is used by CDD (4-bit microprocessor) to retrieve the TOC and Track infos. These signals are not the ones used by Mega CD ASIC to get subcodes.

As for the other diagrams, i think the protocol for reading P-W channel is fairly simple (it's just the diagrams are not very clear):
- there are 98 subcode bytes per sector (1/75 s), each byte being composed of eight (P-Q-R-S-T-U-V-W) channel bits
- the first two bytes are SYNC bytes (S0 and S1), which means the first two bits of P-W channels have a fixed (meaningless) value, this is why it is generally said that each channel is 96 bits per sector
- when DSP detects S0 pattern in subcode byte , it sets SCOR high and starts by outputing bit 8 of SYNC byte (which corresponds to P-channel first bit) then, each time EXCK is asserted (0->1 transition), outputs the next bit (from bit 7 corresponding to Q-channel first bit to bit 1 corresponding to W-channel first bit), then first P-channel bit once again.
- once P-channel bit has been output again, DSP switches to next byte: SCOR remains high for S1 byte then is set low for the next bytes (which correspond to the subcode bytes really holding meaningful P-W bit value, labeled as P1, P2, P3, etc in the diagram)
- operation is repeated for each remaining byte up to the 98th byte then SYNC bytes are detected once again (next sector), etc

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Re: HDD (or flash) instead of a CD, questions...

Post by KanedaFr » Sat Jun 24, 2017 12:03 am

I assumed it was this basic serialization of each of the 2+96 each subdata....
But the datasheet just killed me !

What's not clear is : Is SCOR high for 2 frame (S0 and S1) or only S1 ......

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Re: HDD (or flash) instead of a CD, questions...

Post by HardWareMan » Sat Jun 24, 2017 3:59 am

Every frame of 98 contains not only subchannel data but left and rigth channel samples. I don't remember how much but I guess 6 of each. 44100 / 75 / 98 = 6. 6 * 2 * 2 = 24 bytes.

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Re: HDD (or flash) instead of a CD, questions...

Post by KanedaFr » Sun Jun 25, 2017 9:37 am

HardWareMan wrote:Every frame of 98 contains not only subchannel data but left and rigth channel samples. I don't remember how much but I guess 6 of each. 44100 / 75 / 98 = 6. 6 * 2 * 2 = 24 bytes.
Yes , 2352bytes per sector / 98 frames = 24bytes per frame

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Re: HDD (or flash) instead of a CD, questions...

Post by KanedaFr » Sun Jun 25, 2017 10:06 am

OK, i know understand the meaning of every pin
Image

with some check about the sucode part, I'm now trying to find how all of this is synchronized...

the Communication part is defined by a IRQ every 1/75s (every sector)
:arrow: I read an old MCD dev doc than there is an interrupt on BIOS size at this rate...I'm unable to confirm if it's level 4

The Subcode part is defined by a WFCK of 7.35 Khz (1/137us) (1/75/98 frame)
EXCK seems to be 1MHz...but since it"s driven by MCD, I don't really care
:arrow: I need to see if it's first subcode is in sync with Communication's IRQ. I seems linked to interrupt level 6

The Serial data is audio based (i2s) so
LRCK is 44.1Khz
BCLK is LRCK*24bit*2 = 2Mhz approx.
C2P0 follow BCLK
:arrow: apart to define if first bit is send at the same moment first bit of subcode is send, I see no link between Seria and subcode/comm

======

Since Communication frame is 1/75 and is made of
IRQ + 5 status nibble + 5 command nibble + (working)
I see to way :
1/ Subcode and serial data could be send at any moment during the (working) gap
2/ Subcode and serial data start at the beginning of a Communicationf frame following the one with the relevant command

======

I found the best tool to use for this job but it seems to be out of stock.
I'll try to localize one before I could made some test and measure.
Unless someone already measured serial + comm + subcode data on a same graph ;)

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Re: HDD (or flash) instead of a CD, questions...

Post by HardWareMan » Wed Jun 28, 2017 5:43 am

I have MD1 and I can make some records for you.

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Re: HDD (or flash) instead of a CD, questions...

Post by KanedaFr » Wed Jun 28, 2017 5:27 pm

HardWareMan wrote:I have MD1 and I can make some records for you.
Oh oh!!
Don't say me that, I have a open list ;)

I'd like the timing

1/ about the 4 pins related to SubCode
- WFCK
- EXCK
- SCOR
- SBSO
I really want to see if SCOR is 2 or 1 WFCK long
It would be perfect if logging SBSO could help to identify the sync words (00100000000001 - 00000000010010) but don't know how to trace these...
I would clear the question about S0 before or at start of WFCK

2/ about possible sync between each so a trace of
- IRQ
- WFCK
- BCLK

3/ i keep the log of HOST DATA vs uCON DATA for later : need to finish my ROM tester first ;)
It would help to identify the missing CDD commands


Thanks any or part of these logs ;)

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Re: HDD (or flash) instead of a CD, questions...

Post by KanedaFr » Wed Jun 28, 2017 5:32 pm

Making the log request below ( :oops: ), I suddenly realize the sync words are 14 bits
I don't know how they will be converted to 8 bits (14 bits EFM -> 8 bits data) :(

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Re: HDD (or flash) instead of a CD, questions...

Post by HardWareMan » Wed Jun 28, 2017 6:33 pm

The drive ribbon wire has these signals:
Image
Did it enough for you?

I must make some handy remote pins because MD1 sits above MCD1 and all PCBs are located under MD1 and MD1 apply some force to EXT connector without detent on the opposite end.

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Re: HDD (or flash) instead of a CD, questions...

Post by KanedaFr » Wed Jun 28, 2017 10:24 pm

If you can log every pin, you'll make my day !!
yes, I'm, for now, interesting by the flow on this FFC.

i was planning to remove the faceplate to get access to the pins while power on, not easier ?

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Re: HDD (or flash) instead of a CD, questions...

Post by HardWareMan » Thu Jun 29, 2017 9:09 am

I'm on my way to connect my logic analyzer to CD drive connector:
Image

Code: Select all

 1 - CDCK  (D-->H) CD mechanism control communication clock
 2 - D/M   (D-->H) Mute, output '0' for playback and '1' for mute
 3 - nIRQ  (D-->H) Interrupt request
 4 - nRES  (D<--H) Reset the CD hardware
 5 - HOCK  (D<--H) Host communication clock
 6 - DB0   (D<->H) Data bus bit 0
 7 - DB1   (D<->H) Data bus bit 1
 8 - DB2   (D<->H) Data bus bit 2
 9 - DB3   (D<->H) Data bus bit 3
10 - C2PO  (D-->H) Error flag, outputs '1' when data correction is disabled
11 - BCLK  (D-->H) Audio sample bit clock
12 - SDATA (D-->H) Audio sample serial data
13 - LRCK  (D-->H) Left/Right channel identification clock
14 - DFCK  (D-->H) 16.9344MHz clock output for DAC
15 - N.C.  (D x H) Not connected
16 - N.C.  (D x H) Not connected
17 - EXCK  (D<--H) Sub-code read clock
18 - SBSO  (D-->H) Sub-code data
19 - N.C.  (D x H) Not connected
20 - SCOR  (D-->H) Sub-code sync
21 - GND   (D---H) Digital ground
22 - WFCK  (D-->H) Frame clock
23 - VCC   (D---H) VCC +5V digital power
24 - MVCC  (D---H) VCC +9V motor power
25 - SGND  (D---H) Motor ground
Did you saw this diagrams before (they come from Mega CD 1 manual)?
Image
It seems that 48 bits in transaction, 24 bit for every channel and it is use 16 bit with right align and sign extend (D16...D23 is copy of D15).

Control bus requests:
Image
Image

Also, there would be nice to know what this means:
Image
Last edited by HardWareMan on Thu Jun 29, 2017 10:57 am, edited 1 time in total.

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