GREAT !!!!!Eke wrote:The 4-bit command protocol was actually (partially) reverse-engineered by Stef, there are some notes (CDD_inf.txt I think, can't check now) which describes the commands used by the BIOS, format, etc... I also figured some missing bits (flag indicating music or data, lead-out status indicating the end of CD,...) used by the BIOS and CD player software, you can find some high-level emulation of CDD here (skip to cdd_process function).
this is the strange one....And it's actually made of 10x4-bit words, with the last one being a checksum, first one command id and the rest usually parameters. I've also noticed the BIOS sometmes uses unknown command 0xA before sending PLAY command, I have the feeling it is used for N-Tracks jump configuration.
according 5548's doc, it's 5 nibble... so 5x4bits not 10...
more exactly it's 5nibble CDD->MCD then 5nibble MCD->CDD, using the communication mode you described below
yes, it's clear communication must be perfect.The communication is driven by two clocks: HOCK from Mega CD main ASIC to CDD (4-bit microprocessor, either Sony CXP5084 or NEC UPD7500 on Model 2, Model 1 seems to have HITACHI chip HMCS400 compatible), CDCK from CDD to main ASIC... I think that these are those ones you need to figure out (main ASIC starts driving HOCK signal once the HOCK bit is set in associated CD register).
My main problem is about timing, write handed notes are partialy readable on the manual and it's important to know the exact duration of a HOCK and CDCK pulse...and timing between each nibble.
yep, these ones are "easy" to trace.
CDD also drives the D/M signal (indicates if serial CD data out of DSP is music or data, used by main ASIC to know when to forward SDATA input from DSP to L7883 CDDA DAC/Fader, also reported in one of the CD register bit) and /INT (trigger level 4 interrupt once the last command word has been sent, usually each 1/75 s).
The rest of the signals (serial data, subcode data, serial clocks, C2 error flag, etc) is coming from the DSP (Sony CXD-2500 or -1167 in earlier models) and goes to main ASIC, Sanyo Data Controller (L89510) and CD-DA DAC/Fader (L7883). Sony DSP datasheets have good description of their purpose so it's pretty easy to figure them out. Note that serial CD data (SDATA) is directly connected to the Sanyo CDC chip but goes through the main ASIC before being sent to CD fader, as mentionned above.
My main concern is more SDATA (becoming ODATA and PDATA but it's not really a problem) and timing.
For curiosity and improve my newb electronic skill, why does some of these signals go throught a 74HC245 Octal bus tranceiver ? ESD protection ? to avoid high-impedance (what I call the Z value) ?
ps: 25pin flat cable is so expensive !!! even from china!!