SpritesMind.Net

I've been working on this for some months now, and I'm glad to have the first significant results today.
See the (crappy) video here : http://www.youtube.com/watch?v=tOXrv4ubEbY
It is based on :
- the TG68 core from Tobias Gubener.
- the T80 core from Daniel Wellner.
- glue logic and VDP core from me
It's running on a Terasic/Altera DE1 board.
There's still work to do, but well, I'm quite confident. The whole project will be open-source.

For people who are able to read french, here is my "blog" about this project :
http://heliscar.com/greg/blog.txt

Funny, but I mentioned a project like that last year some time - mentioning the Altera DE1 and 2, how there are two Amiga clone projects done the same way, as well as mentioning those two CPU cores being on the OpenCore site.

I guess great minds think alike.

Please! Keep up the good work. There are plenty of us who are interested in such an endeavor.

Cool project. How much of FPGA capacity is already used?

I've heard a few times from a people who used T80 that it has some bugs.

Woow nice to see the magic VDP on FPGA - cool!

I'd be glad to see VDP in VHDL source that synthesizes in xilinx ise as well Ok, ok verilog will do as well, it's just that I dont speak it

Excellent work and keep it up!

I always wanted to see this done in an open-source way, especially the VDP/YM2612 part
Bravo

PS: tres interessant ton blog

For the moment, there is no sound : nothing about the YM2612, and I've only written the timers of the PSG, as it seems that this is the only part that may cause issues with the the Z80 code, if it was missing.

The TG68 core had a small issue with the MOVEM instruction, now fixed (I've contacted the author about it).
For the T80, I haven't made many tests yet. What are the issues about it ?

The source code is in VHDL.
Some parts are Altera-specific (like the PLL and the dual-port BRAMs), but they could be converted quite easily to their Xilinx counterparts.
I'd like to fix at least the major remaining compatibility issues, then I'll release it.

IIRC, FPGA usage is about 25%.

Torlus wrote:For the T80, I haven't made many tests yet. What are the issues about it ?

I don't know if there are really any issues now, but I recall some discussions about lack of memptr (internal register) and not completely correct timings.

This is pretty cool. I'd be interested in 'enhancing' the capabilities of the Genesis. For example, what could you do if the DACs were really 4-bits per channel instead of 3? The bits are there, the RAM is there, just the LSB in the DAC is missing. Then we'd have 4 palettes of 16 (or 15) out of 4096 colors instead of 512. I wonder if any games fill those bits with meaningful data and would be more colorful on such a modified system. What if the 2612's timer was actually hooked up to something (68K or Z80) - could sound engines have been more powerful? What if there had been a few real, dual port registers in the VDP that the 68K and Z80 could simultaneously access? I can imagine some interesting experiments.

Graz, you don't need an FPGA implementation, i.e. hardware emulator, to try your 'enhancements', it is much easier to do that in any software emulator first. You will have to do this anyway, to create and debug tests/software for the HW version.

Yeah, I guess. I just get a warm fuzzy feeling from coding on real hardware - even if it is an FPGA board! Dunno if anyone looked at http://www.experiment-s.de/en/. These guys don't just 'emulate', they're pin-compatible with the ST. http://www.experiment-s.de/en/pictures/ ... stom-chips . We could do this to the VDP!

Actually, the one enhancement that would be the most useful for the Z80 for audio would be a parallel bank register as opposed to the serial register.

68000 RAM access from Z80 would also be nice.

My implementation supports Z80 access to the 68000 RAM. Apparently it doesn't work on all Genesis revisions.
For a pin-to-pin replacement of the VDP, well, it's not even close, as I had to cope with the board's constraints (i.e use SRAM instead of DRAM), and also TG68 core constraints (it doesn't output the FC0-2 signals of the 68000 required for instance for interrupt acknowledgement).

Actually, the one enhancement that would be the most useful for the Z80 for audio would be a parallel bank register as opposed to the serial register.

IMO an YM2612 timer IRQ would be #1, a sane z80 bank register would be #2.

mic_ wrote:

Actually, the one enhancement that would be the most useful for the Z80 for audio would be a parallel bank register as opposed to the serial register.

IMO an YM2612 timer IRQ would be #1, a sane z80 bank register would be #2.

And both of those are easy/minor changes... what a shock!