Questions about clock signals available on the cart slot

[doragasu]

AFAIK, on the cartridge slot there are two clock signals available:

- CLK (pin B19).
- HS_CLK (pin B15).

I couldn't find too much information about them. CLK is supposed to be the main 68k clock, so I suppose it's 7.67 MHz when working in NTSC mode, and 7.61 MHz when working in PAL mode.

I have read somewhere that HS_CLK is 13.1 MHz. Is this correct? Is it the same for PAL/NTSC? What is this clock used for (I suppose something related to video generation)?

Also if I have a console with the 50/60 Hz mod, does the CLK signal really change depending on the mode, or is this frequency tied to the console hardware (and thus it does not change)?

[TmEE co.(TM)]

VCLK (CLK) is MCLK / 7. MCLK in PAL machines is 53203424Hz and 53693175Hz NTSC machines.
EDCLK (HSCLK) is more fun. It depends on resolution. In H32 mode it is always MCLK / 5 while in H40 it is mostly MCLK / 4 but during blanking it changes to MCLK / 5 for a bit.

[doragasu]

Thanks for the explanation!

There's just one thing that isn't yet clear to me. The clock frequency is tied to the video mode or to the console?

A PAL console with the 60 Hz mod, can generate 7.67 MHz clock signal?

[Mask of Destiny]

EDCLK (HSCLK) is more fun. It depends on resolution. In H32 mode it is always MCLK / 5 while in H40 it is mostly MCLK / 4 but during blanking it changes to MCLK / 5 for a bit.

I was under the impression that EDCLK is the "external" VDP clock which is always that weird mix of MCLK/4 and MCLK/5 rather than the VDP's current clock (which is measurable from the SC pin on VRAM, but not exposed to the cart slot). I haven't measured that myself, but I seem to remember that from one of the discussions of the two mode bits for selecting H40. (i.e. One selects the external clock source rather than the internal divider. The other selects H40 and changes the internal divider to /4).

A PAL console with the 60 Hz mod, can generate 7.67 MHz clock signal?

Nope. As TmEE mentioned, VCLK is always MCLK / 7 regardless of region or video mdoe. The value of master clock is defined by the crystal oscillator installed on the PCB so the only way to change that is to physically replace the oscillator. A standard 60Hz mod will cause the VDP to produce 262 line fields at ~60Hz (though with PAL color encoding), but won't change the master clock.

[TmEE co.(TM)]

EDCLK is generated externally (at least for H40 mode), in MD1 VA0 there's that PCB with oscillator and extra logic on it for that, VA1 and 2 have a PAL type chip for that, VA3 and later move it to bus management chip. The chip also is responsible for generating refresh for the main RAM, and some other RAM related functions I'm not totally sure about.

MD1 VA2 has a different chip in it, I haven't traced out the pinout yet.

[doragasu]

Thanks, everything clear now!

You really know your stuff!!!