Interfacing CMOS 3.3V logic

For hardware talk only (please avoid ROM dumper stuff)
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db-electronics
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Re: Interfacing CMOS 3.3V logic

Post by db-electronics » Tue Oct 20, 2015 1:47 pm

mikejmoffitt wrote:For single-direction communication, actually, isn't a voltage divider acceptable to bring a 5V signal to 3.3V using a suitable ratio? It's the single-resistor series drop that presents problems.
For slow signals it's "acceptable" I guess, in high speed signals it's a bad idea. Slow slew rates are bad for CMOS inputs because the transistors are not operating in cutoff or saturation mode during slow signal transistions and thus power consumption is unnecessarily high. A big advantage of CMOS silicon is that it consumes very little current when the transistors reach a stable condition (i.e. cutoff or saturation [i.e. low or high]). The only time significant amounts of current flow is when they are switching. If you slow down the switching speed your are greatly increasing the current consumption and thus the power dissipation as well.
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