FPGA version

For hardware talk only (please avoid ROM dumper stuff)
HardWareMan
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Post by HardWareMan » Sun Aug 09, 2015 8:36 am

ASIC chips are ready. With handy for probing pins.
Image

I visited the idea: I can experience them out of MD environment. I can make testbench for TA-04 and TA-05. TA-06 too complex for this.

Charles MacDonald
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Post by Charles MacDonald » Mon Aug 10, 2015 1:04 am

I visited the idea: I can experience them out of MD environment. I can make testbench for TA-04 and TA-05. TA-06 too complex for this.
Very nice! Is there a reason why you are looking at the clone chips instead of the originals? Do the clone parts have some interesting or undocumented functions?

HardWareMan
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Post by HardWareMan » Mon Aug 10, 2015 4:36 am

The reason is simple: I don't have any of it. Beside, as I know the TA chipset most accurate clone to original. For example, this TA-04 was replaced by me more than 15 years ago and it still works (burned out arbiter was the reason to change this superclone to onechip MD2 clone):
Image
Anyway, it is better that system was divided into units and testing that units separately is much easier than whole system. You always can assemble those parts into one unit, right?

ob1
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Post by ob1 » Fri Aug 21, 2015 8:22 pm

HAve you guys heard about retro VGS (http://www.retrovgs.com) ?
It's an ARM Cortex 8 (single core, 1GHz) coupled with a 49k EL FPGA.

HardWareMan
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Post by HardWareMan » Sat Aug 22, 2015 4:14 am

ob1 wrote:HAve you guys heard about retro VGS (http://www.retrovgs.com) ?
It's an ARM Cortex 8 (single core, 1GHz) coupled with a 49k EL FPGA.
We don't need yet another emulator. We want a simulator.

ob1
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Post by ob1 » Sat Aug 22, 2015 6:04 am

Of course, of course, I know.
I just wanted to drop the specs.
I was thinking about Kaneda line :
... i'll like to know if a FPGA (or a SoC) version of Genny is possible ? ...
In this "Retro VGS", in what I thought was related, the ARM would be idle, while the FPGA would be the actual Genesis.
Not emulated.
Just FPGA-simulated.

Sorry if off-topic.

HardWareMan
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Re: FPGA version

Post by HardWareMan » Wed Apr 20, 2016 6:01 pm

Some update.
Image
Need to allocate some time to build working DIY prototype.

bastien
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Re: FPGA version

Post by bastien » Wed Jan 25, 2017 12:00 pm

Good works.
It Could be interessting.
It à clone of what chip ?

HardWareMan
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Re: FPGA version

Post by HardWareMan » Wed Aug 23, 2023 5:29 pm

Ok, our team almost done reverse engineering MD ASICs with it's decap. Some of team members was made a hardware level emulator and even FPGA one. Now my turn to finish this project. Finally I done with this:
Image
This is Megadrive that rebuild on custom PCB with possibility to replace the ASICs. I'm gonna recreate the ASICs in CPLD/FPGA and try it in this PCB. There is RAM underneath the ASICs modules.
Image
I found the 1Mx8 5V SRAM chips, so this model able to use 2MB of RAM (from $E00000 through $FFFFFF), but in compatibility purpose it can be reduced to standard 64KB with mirroring. Also I use one half of 32KB chip on the Z80 side. So there avaiable 16KB from $0000 through $3FFF but also can be reduced to standard 8KB with mirroring. VDP mode pin was isolated from region register input at I/O, so able to set all 4 regions on 50Hz or 60Hz VDP mode.
Image
Almost 6 years passed since I posted here pictures of ASICs modules (links to those pictures are dead now) and almost 10 years since I started this project. Now I hope I can finish it, lol.

danibus
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Re: FPGA version

Post by danibus » Mon Sep 04, 2023 5:21 pm

HardWareMan wrote:
Wed Aug 23, 2023 5:29 pm
Ok, our team almost done reverse engineering MD ASICs with it's decap. Some of team members was made a hardware level emulator and even FPGA one. Now my turn to finish this project. Finally I done with this:
Image
This is Megadrive that rebuild on custom PCB with possibility to replace the ASICs. I'm gonna recreate the ASICs in CPLD/FPGA and try it in this PCB. There is RAM underneath the ASICs modules.
Image
I found the 1Mx8 5V SRAM chips, so this model able to use 2MB of RAM (from $E00000 through $FFFFFF), but in compatibility purpose it can be reduced to standard 64KB with mirroring. Also I use one half of 32KB chip on the Z80 side. So there avaiable 16KB from $0000 through $3FFF but also can be reduced to standard 8KB with mirroring. VDP mode pin was isolated from region register input at I/O, so able to set all 4 regions on 50Hz or 60Hz VDP mode.
Image
Almost 6 years passed since I posted here pictures of ASICs modules (links to those pictures are dead now) and almost 10 years since I started this project. Now I hope I can finish it, lol.
Hope you finish. It will be great!
We had mega sg fpga but not sure if you can use their work.

HardWareMan
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Re: FPGA version

Post by HardWareMan » Tue Sep 05, 2023 6:40 am

danibus wrote:
Mon Sep 04, 2023 5:21 pm
We had mega sg fpga but not sure if you can use their work.
I'll use only our decap project as source. I don't want to use any other one's.

AmateurSegaDev
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Re: FPGA version

Post by AmateurSegaDev » Wed Nov 01, 2023 4:50 am

What a beauty, super impressive! Hope you can cross that finish line!

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