Hardware VGM player
Hardware VGM player
I was thinking of gluing together an SN76489AN, an YM2612, a microcontroller (something like an MSP430 or a Tiva C if more juice is needed), an SD slot and some batteries to make a (kind of) portable Genesis VGM files player.
I have started reading VGM files documentation and also some info about SN76489 (the PSG), and doubts about the PSG are starting to arise.
If I understood correctly, there are differences on the noise channel implementation for the PSG included inside the SMS/Genesis VDP and the discrete SN76489AN chip. The Genesis uses a 16-bit LFSR register, and taps bits 0 and 3. The SN76489AN uses a 15-bit LFSR register and taps bits 0 and 1. Is this correct? How does this affect generated sound? Is there much difference? Can it be compensated using any tricks?
I have started reading VGM files documentation and also some info about SN76489 (the PSG), and doubts about the PSG are starting to arise.
If I understood correctly, there are differences on the noise channel implementation for the PSG included inside the SMS/Genesis VDP and the discrete SN76489AN chip. The Genesis uses a 16-bit LFSR register, and taps bits 0 and 3. The SN76489AN uses a 15-bit LFSR register and taps bits 0 and 1. Is this correct? How does this affect generated sound? Is there much difference? Can it be compensated using any tricks?
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"periodic" mode on the noise channel has 6.66...% duty cycle rather than 6.25% which is pretty noticable.
White noise is not really different audibly from the shorter register.
White noise is not really different audibly from the shorter register.
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Thanks for the replies!
Functionality of the PSG doesn't look complex, so I might try implementing it using four microcontroller timers tied to output pins and some extra hardware for mixing (and maybe also a 16-bit shift register), but I don't know if it will sound the same because of the decay time of the chip output and some other artifacts thay I might not be considering. Do you think re-implementing it is worth the effort?
PS: I have just ordered the chips off ebay, so I might start experimenting in a month or so (when they arrive).
Is it really that noticeable? Is "periodic" noise often used for game tunes? (I don't care if it is mainly used for SFX, as I'll only use this "player" for game tunes). Are there any tricks to compensate this difference? (I suppose there are not, but doesn't hurt to ask).TmEE co.(TM) wrote:"periodic" mode on the noise channel has 6.66...% duty cycle rather than 6.25% which is pretty noticable.
White noise is not really different audibly from the shorter register.
Functionality of the PSG doesn't look complex, so I might try implementing it using four microcontroller timers tied to output pins and some extra hardware for mixing (and maybe also a 16-bit shift register), but I don't know if it will sound the same because of the decay time of the chip output and some other artifacts thay I might not be considering. Do you think re-implementing it is worth the effort?
PS: I have just ordered the chips off ebay, so I might start experimenting in a month or so (when they arrive).
I have started experimenting with the YM2612. So far I have only connected power and GND pins to 5V, and the buses (D0~D7, A0, A1, CS, RD, WR, IC) to GPIO pins in the Stellaris Launchpad. These pins are not configured (so right now they are HighZ). I have neither connected the 7,67 MHz clock to the chip. Then I have powered the chip just to check it doesn't explode, and to my surprise, it becomes VERY hot, it is uncomfortable to touch. I have double checked every connection and I cannot find an error, power and GND pins are OK.
Is it normal it becomes so hot when it is not even working? I'm wondering if it might be damaged because of not applying signals to the buses, but I don't think so.
Is it normal it becomes so hot when it is not even working? I'm wondering if it might be damaged because of not applying signals to the buses, but I don't think so.
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Tie the clk signal to GND and see if it still gets really warm. The chip does get fairly warm in MD, does it get hotter than that in your application ?
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I have never touched it while working in the MD, so I don't know. As I was not driving CE, RD and WR signals, I suspect maybe all of them could be active, and I'm wondering if this could cause trouble.
I want to write code to initialize the chip and set these signals to disabled state ('1'). Unfortunately I have no time ATM. I'll write here the results.
I want to write code to initialize the chip and set these signals to disabled state ('1'). Unfortunately I have no time ATM. I'll write here the results.
By the way, is there any timing information on the chip? How much time do I have to assert the IC signal to reset the chip? And the same about CE, RD WR and data (D0~D7) signals.
EDIT: I'm browsing an YM3438 japanese datasheet. Assuming timing is the same for YM2612, to write data I have to:
1.- Write A0 and A1, and then wait at least 10 ns (Tas).
2.- Clear CS and WR, and put data in D0~D7, then wait at least 200 ns (Tcsw and Tww).
3.- Release CS and WR, and wait at least 10 ns (Tah).
4.- Repeat for the next write. Twdh of the last write is met because of the Tah of the last write plus the Tas of the new write.
Also to reset the chip, IC signal must be pulled low for at least 192 cycles.
Edit 2: I have just noticed I have to wait 17, 83 or 47 cycles between two consecutive writes. As the datasheet is in japanese, I don't know when I have to wait 17 cycles, when I have to wait 83 cycles or when I have to wait 47 cycles. Any help with this?
EDIT: I'm browsing an YM3438 japanese datasheet. Assuming timing is the same for YM2612, to write data I have to:
1.- Write A0 and A1, and then wait at least 10 ns (Tas).
2.- Clear CS and WR, and put data in D0~D7, then wait at least 200 ns (Tcsw and Tww).
3.- Release CS and WR, and wait at least 10 ns (Tah).
4.- Repeat for the next write. Twdh of the last write is met because of the Tah of the last write plus the Tas of the new write.
Also to reset the chip, IC signal must be pulled low for at least 192 cycles.
Edit 2: I have just noticed I have to wait 17, 83 or 47 cycles between two consecutive writes. As the datasheet is in japanese, I don't know when I have to wait 17 cycles, when I have to wait 83 cycles or when I have to wait 47 cycles. Any help with this?
Found a YM2608 japanese datasheet. I suppose this should be nearer to the YM2612 than the YM3438. Most of the timing details are the same, but there are different diagrams for FM, SSG and ADPCM reads/writes. Also it looks like there are no restrictions on consecutive reads/writes. Too bad it's japanese only.
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Index writes need 17 cycles and Data writes need 47 or 83 cycles until next. How many depends on what registers you are writing. Most require 83
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3438, 2203, 2608 datasheets all say same things as far as write access goes.
I am not at home to check what register ranges have slow and which faster access. I recall all registers that deal with individual channels are 83 cycle ones.
Index writes are the register address writes indeed.
I am not at home to check what register ranges have slow and which faster access. I recall all registers that deal with individual channels are 83 cycle ones.
Index writes are the register address writes indeed.
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