Hey all, im new here and a genesis/megadrive noob. Im still learning the hardware and I have a few questions.
1) What does the SEGA 315-5345 IC do? Im guessing since it has the EDClk pin as well as a HSYNC pin it helps convert the video to PAL and NTSC formats.
2) Did the motherboard versions previous to using SEGA 315-5402/315-5433 IC's not have TMSS? or was TMSS implemented in a different fashion?
A couple of questions about the genesis hardware
A couple of questions about the genesis hardware
Last edited by uprock7 on Wed May 01, 2013 6:55 pm, edited 2 times in total.
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Mask of Destiny
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I don't have much of a guess as to what 315-5345 does, but I doubt it has much to do with PAL vs. NTSC. It would be a bit easier to guess if I knew which signals were outputs on the chip.
As for your second question, the page here: http://wiki.megadrive.org/index.php?tit ... gory:Chips
suggests that 315-5402 didn't contain a TMSS, but the 315-5433 did (well a broken implementation anyway). Before the 315-5402, it looks like I/O and bus arbitration were split into two separate chips: 315-5308 and 315-5309.
As for your second question, the page here: http://wiki.megadrive.org/index.php?tit ... gory:Chips
suggests that 315-5402 didn't contain a TMSS, but the 315-5433 did (well a broken implementation anyway). Before the 315-5402, it looks like I/O and bus arbitration were split into two separate chips: 315-5308 and 315-5309.
From the pinout, it seems 315-5345 is responsible of EDCLK generation (external dot clock in H40 mode, based on HSYNC and MCLK inputs) and 68k RAM refresh. It only exists on VA2 model apparently, which afaik do not exist in PAL version, and was later included with bus arbiter (315-5308) into 315-5364.
On VA1 models (japan only ?), there was apparently a previous version of that chip (315-5339), and, according to the pinout posted here:
viewtopic.php?p=14470
,both chip probably also handle IA14 RAM signal in M3 compatibility mode. The difference seems to be the addition of BGACK in the later version, probably to fix some VDP DMA timings issues when taking the 68k bus.
On VA0 models (japan only), there was instead a custom little board that was apparently added after mainboard production, which apparently has the same functions of these later chips.
I guess it was some kind of bugfix circuit to take care of some early production issues (distorted video, RAM problems, etc)
On VA1 models (japan only ?), there was apparently a previous version of that chip (315-5339), and, according to the pinout posted here:
viewtopic.php?p=14470
,both chip probably also handle IA14 RAM signal in M3 compatibility mode. The difference seems to be the addition of BGACK in the later version, probably to fix some VDP DMA timings issues when taking the 68k bus.
On VA0 models (japan only), there was instead a custom little board that was apparently added after mainboard production, which apparently has the same functions of these later chips.
I guess it was some kind of bugfix circuit to take care of some early production issues (distorted video, RAM problems, etc)