SpritesMind.Net

Cool that you have possibility to test that !!! Perhaps it will be more precise to make a loop reading hv counter and when the interrupt occurs to know the last value readed? Because with this methode you have latency between the moment the h-int occurs and the moment the register is readed (308 MCL...

What i want to do is to test vdp timings with this cart.
Is it possible to stock result in SRAM and transfering the data of the SRAM after tests on the pc for analysing?

I'm searching sega genesis programmable card to do tests on real hardware.
I don't know where to buy it.
I found this website :

http://www.tototek.com/old.php

Does someone know if this is a good website?
Are they other website to buy such item?

Thank you

My solution is bad.
The only way to be sure is to have the value of hcounter when horizontal interrupt occurs, but i don't have programming cart

Other supposition :

To determine where hblank flag is set to ON/OFF we have only h-counter value.
So imagine that in fact the h-counter begins to 0 after left border at the start of active display (as Charles MC Donald said in his doc) .
So The problem is gone out and we respect his values ...

With hblank flag end at h-int + 860 it's correct.

So with hblank cleared at H-int + 988 the game doesn't display correctly? The only difference is that for me this is the first bar that is wrongly displayed. Here is the reason : ROM:00000F54 HInt: ; DATA XREF: ROM:00000070o Start Length ROM:00000F54 tst.w ($FFFFF644).w 309 84 ROM:00000F58 beq.w loc...

Have you the possibility eke to test this hblank flag timings (h-int + 406 -> hblank flag = 1, h-int + 988 -> hblank flag = 0) in genesis plus to see if you have the same problem with the first line of blue bar?

I set this timings in my emulator. The delay between H-INT and HBLANK=0 give me problem with the blue bar of sonic 2. I already had this problem before. extract of my previous response to this topic : H-INT : 0 HBlankStart = H-INT + 130 MClks HBlankEnd = H-INT + 130 MClks + 860 Mclks So the delay be...

So interrupt occurs at H_counter = 0xF9.
Our schemas are exactly the same

Yes.
I will compare my schemas with yours.

Thank you for all.

Another question :
Gorge in his post says that line 31 in NTSC is the first drawn line.
There is a relation between vcounter value?

I forgot to correct them. Now is ok. For V-INT interrupt, i calcul it happens juste before H-COUNTER = 0xFA. I explain : - According to Jorge Nuno Delay between H-INT and V-INT is 788 MCLKS. - According to my schema, delay between H-INT and H-BLANK END is 988 MCLKS - So V-INT happens 200 MCLKS befor...

Everything seems to feet correctly.
I corrected the schema.

I made this schema to detail VDP timings in H40 mode : - 320 "H40 dots" (H40DCLKS) (Active Display) - 26,5 (correct to 26) "H40 dots" (H40DCLKS) (Back border, Back porch, Start HSync) - 30 "H32 dots" (H32DCLKS) (End HSync, Start front porch) - 43,5 (correct to 44) "H40 dots" (H40DCLKS) (End front po...