SpritesMind.Net

I think this discussion lack clarifying objectives. Is it "cycle accuracy" what are you aiming for? Is it speed? Perhaps a mix of both? And then what is “cycle accuracy” really?, as its name says should be that at the end of every cycle the chip status is the same as emulator status, but I bet no em...

This is a pretty good answer for this last dilemma:

https://forums.nesdev.com/viewtopic.php ... 86#p239757

The only thing is MD/Genesis has a limited cpu and ram, compared with modern ones, so the solution has to be restricted to something smaller.

@FireRat, so you are obtaining a word/long from an odd address the seeing if the Address Error Exception fires? That's easy to detect on a emulator ("address & 1") and at least some emus check it (Reggen comes to mind). You still may be better off not trying to detect emulators but rather the partic...

Ok, knowing that you are aiming for single thread and cycle accuracy my first approach would be: void emulator() { int commonCycles = 1; for(;;) { run( commonCycles ); // This doesn't work, but the idea is to adjust the time slice to // speed up/down depending on the cpu power we got if( plentyOfTim...

Thanks for bring this subject up, it’s really interesting. My major point is I need more time to think about all this because bring a lot of knowledge altogether. But so far my developing thoughts are: General theory says you should make a difference between a thread and a workload: threads should b...

In gcc you can write inline assembly or compose an assembly file, both ways works the same really. Inline assembly: + fully interlockable with C - more verbose - you NEED to know the use of the key words “__asm volatile” and “__asm” - you need to use implicit params (%), and how they work ("=>a", "=...

Just a sudden inspiration: "When in doubt just ask the Chinese for news".

I haven't check how the VPD works but judging by how the 68k does: VDP has to signal !BR (bus request) and wait for !BG (bus grand); the same when Z80 access main memory. Also !DTACK could be used to put the cpu in a wait state, the problem is the address bus is being used by the cpu while !DTACK is...

That’s like ignoring the father of all signals, what you say is truly reality breaking.

I just booked it in my “to do” list to study and resolve once for all this affair.

Sik wrote: ↑

Mon May 13, 2019 7:01 pm

1) VDP has a complete disregard for paying attention to signals for memory accesses

Are you saying DTACK signal (and his companion, I don't remember the name) is ignored ?

That's hard to believe.

A static frame buffer on a game? I don't think is possible.

No, the 7.67 Mhz 68000 is actually * slower * than the 2.68 Mhz 65C816 at accessing memory... However, the 65xx cannot transfer memory on every clock, so that's moot. Stef is correct, 65816 transfers 1 byte per 1 cycle, non-stop if needed, no problem. You have to remember that the 68000 takes multi...

Oh! There is no instruction prefech on the 65c816, now this makes sense. So this is really a read cycle of one cycle.

TmEE co.(TM) and Stef, If that’s to be believed: http://laughtonelectronics.com/Arcana/Visualizing%2065xx%20Timing/Visualizing%2065xx%20CPU%20Timing.html data bus is in use by two cycles. By reading earlier you are only imposing more speed on RAM. In other words, can you read a byte per cycle? Is NO...

I'm sorry Chilly Willy, you were saying exactly what I think, I just read "read memory of 1 cycle" and go berserk.

The data is ready at the end of the first cycle, but can't be used until next cycle; so it's two cycles from my point of view.