Search found 256 matches
- Tue Sep 18, 2018 9:00 am
- Forum: Hardware
- Topic: Some questions about Saturn HW
- Replies: 25
- Views: 40687
Re: Some questions about Saturn HW
The SH2/VDP1/VDP2/SCU clocks are generated by a PLL (IC20), which uses 14.318MHz * 2 = 28.6 MHz in 352px mode. In 320px mode, it runs the frequency through a 1708/1820 divider to get 26.8MHz. SCU DSP runs at half of that. In PAL units it uses a 17,734 MHz crystal and it is run through a 910/1135 di...
- Mon Sep 17, 2018 2:43 pm
- Forum: Hardware
- Topic: Some questions about Saturn HW
- Replies: 25
- Views: 40687
Re: Some questions about Saturn HW
Thanks for this complete answer ! So it could be possible to overclock the saturn but not without affecting video signal?
- Sat Sep 15, 2018 9:19 am
- Forum: Hardware
- Topic: Some questions about Saturn HW
- Replies: 25
- Views: 40687
Re: Some questions about Saturn HW
Hello everyone.
I'm taking benefits of this post to ask a a question about saturn hardware.
How is handle the SH2 clock?
The SH2 generates its own clock and output it to the vdp?
SH2 takes an input clock derived from a master clock (like the 68000 is Master Clock / 7 for a sega genesis)?
Thanks !
I'm taking benefits of this post to ask a a question about saturn hardware.
How is handle the SH2 clock?
The SH2 generates its own clock and output it to the vdp?
SH2 takes an input clock derived from a master clock (like the 68000 is Master Clock / 7 for a sega genesis)?
Thanks !
- Thu May 26, 2016 12:26 pm
- Forum: Video Display Processor
- Topic: VDP VRAM access timing
- Replies: 40
- Views: 120877
Re: VDP VRAM access timing
If i undst good the shema from Nemesis : Slot 12 : When Hsync go high the line start to be drawn on tv Slot 6 to 13 : The first left scrolled 2 cells are fetched and output to internal line buffer => During this period 2 cells fulling with background color are output to tv (left border) Slot 14 to 2...
- Sun May 08, 2016 5:34 pm
- Forum: Megadrive/Genesis
- Topic: Genesis Vdp Global Documentation
- Replies: 2
- Views: 3839
Re: Genesis Vdp Global Documentation
Thanks for the links
- Sat May 07, 2016 8:49 am
- Forum: Megadrive/Genesis
- Topic: DMA and FIFO
- Replies: 11
- Views: 16106
Re: DMA and FIFO
Thanks for your answer.
Does the latency affect the dtack signal from vdp to 68K when perform a read or write operation?
Does the latency affect the dtack signal from vdp to 68K when perform a read or write operation?
- Fri May 06, 2016 3:50 pm
- Forum: Megadrive/Genesis
- Topic: DMA and FIFO
- Replies: 11
- Views: 16106
DMA and FIFO
Does The DMA is using the external access slot to transfert data from/to vram?
What happen for example if there is a dma fill or dma copy and the 68k try to access vram?
What happen for example if there is a dma fill or dma copy and the 68k try to access vram?
- Wed May 04, 2016 12:33 pm
- Forum: Megadrive/Genesis
- Topic: Genesis Vdp Global Documentation
- Replies: 2
- Views: 3839
Genesis Vdp Global Documentation
I would like to know if exist a documentation compiling all informations about the genesis vdp (description of all slot, register latch timing, interrupt timing ...).
- Mon Jul 20, 2015 4:06 pm
- Forum: Video Display Processor
- Topic: VDP VRAM access timing
- Replies: 40
- Views: 120877
If i take your notes Nemesis. From Access Slot 6 to 13 (2 cells Border) datas from 2 first displayed cells are latched and renderer in a 2 cells buffer. During Access Clots 14 to 21 (2 first displayed cells) pixels are generated from the buffer and during this time datas from displayed cells 3 and 4...
- Tue Jul 14, 2015 9:20 pm
- Forum: Exodus
- Topic: Exodus 2.0 + Open Source Release
- Replies: 105
- Views: 308091
- Mon Jul 13, 2015 10:51 am
- Forum: Megadrive/Genesis
- Topic: Question About Sonic 2
- Replies: 4
- Views: 3779
- Sat Jul 11, 2015 6:11 am
- Forum: Megadrive/Genesis
- Topic: Question About Sonic 2
- Replies: 4
- Views: 3779
- Fri Jul 10, 2015 4:38 pm
- Forum: Megadrive/Genesis
- Topic: Question About Sonic 2
- Replies: 4
- Views: 3779
Question About Sonic 2
Does anyone knows if Sonic 2 Z80 access M68K memory via bank space mecanism? Or all datas are loaded in Z80 Memory?
I'm currently testing The Z80 part in my emulator.
Does exist some Z80 test rom?
I'm currently testing The Z80 part in my emulator.
Does exist some Z80 test rom?
- Fri Jun 26, 2015 6:49 pm
- Forum: Exodus
- Topic: Exodus 2.0 + Open Source Release
- Replies: 105
- Views: 308091
- Sun Jun 07, 2015 6:34 pm
- Forum: Hardware
- Topic: I/O Ports read upper byte
- Replies: 1
- Views: 8629
I/O Ports read upper byte
Does anyone knows what happens when reading higher byte of I/O ports?
In doc they said that in case of byte access only lower byte is meaningful (mean odd adress).
In doc they said that in case of byte access only lower byte is meaningful (mean odd adress).