SpritesMind.Net

bump There's 1 more serious issue, when overclocking the CPU, this: http://trapalhadas.no.sapo.pt/MDacesses/20042009149.jpg Yellow is /AS signal, Blu is /DTACK. (using Edclk for the 68k), wave persistence is 5 seconds. As it can be seen, the access times vary between 125ns and ~25ns, due to the fact...

Anyone knows what /CAS2 and /RAS2 do? Are they DRAM signals? /CAS2 seems to be used in conjunction with /ASEL and /ROM (or /CE0) : /ROM or /CE0 acting as a row address strobe, /ASEL toggling the rows/columns multiplexer, and /CAS2 as the column address strobe. Notice that they are asserted in the s...

Can I externally sink TH low on control port 2 (or 3) so it triggers a level 2 int, while TH on port 1 is an output (standart controller)?

I need to set bit #3 of VDP register #$0B and bit #1 of register #00, yes?

PAL have little slower clocks in everything becuase the oscillator is 53.2034MHz instead of 53.69??MHz in NTSC machines

Z80 is 53.2034/15 MHz
68k and YM are 53.2034/7 MHz
(in PAL MDs)

interesting... you mean EDCLK is an input for the VDP, not an output ? then it makes sense yes but what could be 315-5433, never heard of this part before (at least it is not on Model 1 schematics) ? It's model1 - TMSS (VA6 board), ext port not present but reserved. The chip is a squared PQFP like ...

Not yet, I think that statement is somwhat wrong... Because if you set bit5 of Mode Set Register #4, Edclk will be always M/4 (hsync signal will be '1' all the time) In H32: (I'm working with a 2Ch+Ext osc now...) The pixel clock never changes, its always ~5.319MHz http://trapalhadas.no.sapo.pt/MDvi...

Remember that there is the pixel clock at ~6MHz... Every video signal is synchronous with it's rising edges, but for some reason everyone forget it. In H40 it's nothing more than Edclk/2, which means that during H pulses it changes rate. Unfortunately, my current oscilloscope doesn't have the bandwi...

Anyway, I'm lost... What was this for? About the /TIME memory accesses, and VDP ones, the read/write cycle timing can be visualized on a scope, to see if it is different or not...

Second, we can made some big counter wich will count M68K clocks and will reset with M68K. Outputs of this counter can be passed thru 74x245 bus former to data line at some address. So, software always can get number of ticks goes from start of program (reset). I think it is more easy. And I can ma...

Umm playing with deflection coils huh? I think the MD approach is more useful: multichannel, grid, signal measurements, does not limit bandwidth by itself (limited by the ADCs and FIFOs), trigger options, signal operations (+/-/Avg/FFT),software updates to add features, dumping options, and of cours...

Wow that's just insane ... You are not thinking using a megadrive + cart with some ADCs to do that are you?


Damn offtopic

If you are in university, maybe you have the chance to use this kind of equipment in some occasions, I'm like you too, I only have a cheap multimeter + soldering iron (it has a tip like a screwdriver ) at home I can only burn/erase my eprom there, too.

Which clock will you manually give to the VDP? EDclk? or M? or both :D ? Remeber that VRAM dies if you supply a clock too low, around /3, most likely. The video signals are not so important if you hook a logic analyser on VD bus and trigger it on DTACK \__ With some luck the VDP works without VRAM, ...

If the 68K is overclocked you can't predict the memory access delays, becuase AS is strobed using the default clock and DTACK is driven low with the default clock too. Any other clock you supply to it, the 68K will be out of phase with the events of the bus-decoder, and could potentially lead to inv...

You have a NAND with an input at 0 level in the middle, that gives an «always 1» And there is 1 (at least) redundant port... Man I never saw a difficult-following schematic to do a simple thing