SpritesMind.Net

Ahh ok, so it's an universal fpga devboard. Bonus points for circuit reutilization there.

Forget about the OE being low, it is CE that does that on a DMA, it's low for a burst while OE toggles. My bad here

Thanks for the answers. Another question: Why is it a 2-board setup :P And yes ISE sucks in comparison with Quartus.. it's just so bloated everywhere. Also notice that Xilinx CPLDs have stopped in time, even though they have limited usability. On a DMA or z80 access, how do you check if a new access...

Let me say this first: this is AWESOME. Now that it's out of the way I have a few questions: - Was a 4-layer board really necessary? doesn't seem the case to me, I've done heavier and denser stuff on 2 sided boards, even with BGA (50ball memory IC). - Xilinx is expensive. I have the impression that ...

No, the 68k has byte RW strobes, not just writes: UDS and LDS. The cart slot is given 2 write strobes (LWR and UWR) and they come from the VDP. They are asserted both from 68k writes and z80 writes. Using time to mask all rom in place for a 4MB ram will give you a big problem: suddenly the 68k loses...

Aha, so it was the MSB instead of the LSB as I thought initially.. damn

No the VDP is still a goddamn virgin, noone poked at it yet. It's loooong overdue :P That Spartan 3E has 8672 "slices" [Xilinx terminology] Each S3E slice has 2 LUT-4s and 2 FFs, so I guess it would be equivalent to an altera chip with 17344 LEs... maybe I dunno. The chips may have a different inter...

Problem is that the CRAM and VSRM are internal.. There's a bunch of work from Nemesis on interpreting VDP inner behaviours, but it's doing indirectly. We have no direct access to internal stuff, not untill a chip is decapped and analysed Tile pointers always go from 0 upto 7FF. On interlace it's the...

That looks correct

I have a XC3S1200E, not sure if this project fits inside... probably not.
How many LEs?

Oh, it uses the vertical flip flag to modify the address generator. Inside the if VF= '1' then.. you have to add another if statement for the interlace flag The "multiplication stage" is nothing more than the concatenation of 0s to the right side :P I saw your last code snippet... try it, I guess.. ...

I could be that you're assigning multiple values to the same bus even though there's no bit collision.. You can try this HEXVALUE <= FM_DI & PSG_DI; The & is a concatenation operator, it will put the FM byte in the upper half because your bus is 15 downto 0 You take the nametable index and process i...

On interlace mode 2 tiles become 8x16 pixels, the nametable tile pointer is now halved, and of course only odd or even lines are rendered (though you may output them all as if it were a 320x640 resolution).
I think horizontal line scrolling affects now pairs of lines 0/1, 2/3, 4/5, etc

Wait, you're saying that the DMA transfers are in sync with VClk? doesn't make sense to me as they seem to pulse at 150/300ns... These are Cart slot /CAS0 (yellow) and /CE_0 (blue) http://img.ctrlv.in/img/52365f49ad2cf.jpg Notice the access cycle time is about 300ns, which would give a running clock...

That's the order of a CBR cycle. Then yes you can connect them directly, just need a bunch of 74HC157s to mux those address lines with S connected to RAS or to ASEL, designer's choice :P Too bad it's only from 0x600000+ but ehh, can't have everything... Speaking of which, the cart slot should have i...

For the address selection (which is what the ASEL is probably meant for judging by the name it bears) the RAS signal can be used most of the times to select the row/column of an external mux: Since drams typically need a row address hold time of about 10ns (or sometimes less), we can take advantage ...

While this info is pretty much overwhelming I'll just say that the test rom failed on my GenIII on tests 6, 25, 34, 74, 77, 80, 83, 86, 89, 92, and 95 The extra VScroll memory may be related to the fact why this particular model isn't affected by the 2-cell VScroll bug on column -1 (or maybe not) Bu...