SpritesMind.Net

New info! Using MIDIbox Quad Genesis and the test modes, I have confirmed the internal order of calculation of operators and channels. These tests were performed on hardware (DIP) YM3438s, which is what I have in my synth. You may say this isn't helpful, as this is neither YM2612 nor whatever's in t...

What is suspicious for me, that all stages implemented as "process" in your code. I thought, it should be concurent, and what actually process is shift buffer that does shift. Keep in mind that in VHDL, all statements in a process are executed sequentially, but in zero time. In reality, the stateme...

I'm not sure why you're trying to figure out the pipeline stages, I've already finished that, the information is in my VHDL operator unit at https://github.com/sauraen/YM2612/blob/master/Source/operator.vhd . There are five stages that actually do work, one that just stores the value, and an additio...

From an emulation perspective, the only way it probably matters involves how the order of processing interacts with the funky register file and register write timing. And that only matters for emulators that actually care about write timings, i.e. Exodus. I think I know why it's 3 clocks of zero an...

Is there in fact an internal /6 divider on the clock line Yup, this has been known for a while. It takes 24 INTERNAL clock cycles to evaluate everything, which is 144 external clock cycles. Wasn't the MAME implementation originally somewhat generic in that could emulate multiple members of the OPN ...

What I mean is that behind all this crazy pipelining in the YM2612 is a number of control units which each have exactly the correct number of delays in each signal so that all the signals used in each channel are correct. There's no question that this is implemented correctly in the YM2612, and the ...

all chanels should be indpendent Yes, I wasn't saying they weren't. Obviously parameters of one channel don't affect the others (at least not until we get to the DAC...). The order of evaluation of the channels won't make any difference to whether a software implementation produces a sample-accurat...

Is it me or are you all overcomplicating things? Yes, we are, in so far as I can't even think of a test sound that would sound audibly different whether modulators were delayed by a cycle or not. Can't you just do it like the YM2612 and just process one operator at a time? the YM2612 doesn't exactl...

Ouch I don't have time right now for a giant answer, but I think this is what you're missing. Please also refer to my operator unit VHDL code I linked in the previous post. The operator unit, like all the other units in the YM2203, is pipelined. It takes six internal clock cycles to compute the out...

I took the bait and started an analysis of the control unit that generates the signals specifying which values are added during which cycles (the op_algorithm_ctl signal in my VHDL version of the operator unit ). Here's the results so far: All these observations are directly from the YM2203, not the...

@CountSymphoniC Thanks! Not to derail the thread or shamelessly self-promote, but here's the current state of the MIDIbox Quad Genesis project. The MBHP_Genesis boards which I designed, each of which holds one YM2612/YM3438 and one SN76489 and provides appropriate glue logic for a parallel interface...

FWIW here's the timing in MIDIbox Quad Genesis : http://svnmios.midibox.org/filedetails.php?repname=svn.mios32&path=%2Ftrunk%2Fmodules%2Fvgm%2Fvgmplayer.h http://svnmios.midibox.org/filedetails.php?repname=svn.mios32&path=%2Ftrunk%2Fmodules%2Fvgm%2Fvgmplayer.c This driver was developed on the first ...

I apologize for my absence from this thread for the last couple months, I've been very busy towards the end of this semester with several things (including making a complete 8-bit microprocessor at the transistor level for a VLSI class--46 instructions, 50 MHz!) I've finally finished my VHDL equival...

Okay, here's a thread about the decapping: viewtopic.php?f=13&t=2191

This is a continuation of discussion about decapping from the YM2612 thread at http://gendev.spritesmind.net/forum/viewtopic.php?f=24&t=386&start=750 I am a post-bac electrical engineering student at a major university in the US, and for my independent study research this semester I've been reverse ...